Typical at TA = 25°C, V
參數資料
型號: AD1380KD
廠商: Analog Devices Inc
文件頁數: 6/12頁
文件大?。?/td> 0K
描述: IC ADC SNGL 16BIT 32-CDIP
標準包裝: 1
位數: 16
采樣率(每秒): 50k
數據接口: 并聯(lián)
轉換器數目: 1
功率耗散(最大): 900mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 32-DIP(0.900",22.86mm)
供應商設備封裝: 32-BBDIP-H
包裝: 管件
輸入數目和類型: 16 個單端,雙極;16 個單端,單極
AD1380
Rev. D | Page 3 of 12
SPECIFICATIONS
Typical at TA = 25°C, VS = 15 V, 5 V, combined sample-and-hold ADC, unless otherwise noted.
Table 1.
AD1380JD
AD1380KD
Model
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUTS
Bipolar
±2.5
V
±5
V
±10
V
Unipolar
0 to 5
V
0 to 10
V
DIGITAL INPUTS1
Convert Command
TTL-compatible, trailing edge of positive 50 ns (min) pulse
Logic Loading
1
LSTTL Loads
TRANSFER CHARACTERISTICS2
(COMBINED ADC/SHA)
Gain Error
±0.1
±0.1
Unipolar Offset Error
±0.05
±0.05
% FSR
Bipolar Zero Error
±0.05
±0.05
% FSR
Linearity Error
±0.006
±0.003
% FSR
Differential Linearity Error
±0.003
% FSR
Noise
10 V Unipolar
85
μV rms
20 V Bipolar
115
μV rms
THROUGHPUT
Conversion Time
14
μs
Acquisition Time (20 V Step)
6
μs
SAMPLE AND HOLD
Input Resistance
4
Small Signal Bandwidth
900
kHz
Aperture Time
50
ns
Aperture Jitter
100
ps rms
Droop Rate
50
μV/ms
TMIN to TMAX
1
mV/ms
Feedthrough
80
dB
DRIFT (ADC AND SHA)5
Gain
±20
ppm/°C
Unipolar Offset
±2
±5
±2
±5
ppm/°C
Bipolar Zero
±2
±5
±2
±5
ppm/°C
No Missing Codes (Guaranteed)
0 to +70 (13 Bits)
0 to +70 (14 Bits)
°C
DIGITAL OUTPUTS (TTL-COMPATIBLE)
All Codes Complementary
5
LSTTL Loads
Clock Frequency
1.1
MHz
POWER SUPPLY REQUIREMENTS
Analog Supplies
+14.5
+15
+15.5
+14.5
+15
+15.5
V
14.5
15
15.5
14.5
15
15.5
V
Digital Supply
+4.75
+5
+5.25
+4.75
+5
+5.25
V
+15 V Supply Current
25
mA
15 V Supply Current
30
mA
+5 V Supply Current
15
mA
Power Dissipation
900
mW
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