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參數(shù)資料
| 型號： | AD1674B |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit 100 kSPS A/D Converter |
| 中文描述： | 12位100 kSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 255K |
| 代理商： | AD1674B |
AD1674
REV. C
–5–
(for all grades T
MN
to T
MAX
wth V
CC
= +15 V
6
10% or +12 V
6
5%,
V
LOGIC
= +5 V
6
10%, V
EE
= –15 V
6
10% or –12 V
6
5%; V
IL
= 0.4 V,
V
IH
= 2.4 V unless otherwse noted)
SWITCHINGSPECIFICATIONS
CONVE RT E R ST ART T IMING (Figure 1)
J, K, A, B, Grades
T Grade
Min
Parameter
Symbol Min T yp
Max
T yp Max Units
Conversion T ime
8-Bit Cycle
12-Bit Cycle
ST S Delay from CE
CE Pulse Width
CS
to CE Setup
CS
Low During CE High t
HSC
R/
C
to CE Setup
R/
C
Low During CE High t
HRC
A
0
to CE Setup
A
0
Valid During CE High t
HAC
t
C
t
C
t
DSC
t
HEC
t
SSC
7
9
8
10
200
7
9
8
10
225 ns
μ
s
μ
s
50
50
50
50
50
0
50
50
50
50
50
50
0
50
ns
ns
ns
ns
ns
ns
ns
t
SRC
t
SAC
RE AD T IMING—FULL CONT ROL MODE (Figure 2)
J, K, A, B, Grades
Symbol Min
T Grade
Min
Parameter
T yp
Max
T yp Max Units
Access T ime
Data Valid After CE Low
t
DD
t
HD
1
75
150
75
150 ns
25
2
20
3
25
2
15
4
ns
ns
Output Float Delay
CS
to CE Setup
R/
C
to CE Setup
A
0
to CE Setup
CS
Valid After CE Low
R/
C
High After CE Low
A
0
Valid After CE Low
t
HL5
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
150
150 ns
50
0
50
0
0
50
50
0
50
0
0
50
ns
ns
ns
ns
ns
ns
NOT ES
1
t
DD
is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0
°
C to T
MAX
.
3
At –40
°
C.
4
At –55
°
C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
T est
V
CP
C
OUT
Access T ime High Z to Logic Low
Float T ime Logic High to High Z
Access T ime High Z to Logic High
Float T ime Logic Low to High Z
5 V
0 V
0 V
5 V
100 pF
10 pF
100 pF
10 pF
t
HEC
CE
STS
DB11 – DB0
A
0
CS
__
R/C
_
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
t
C
t
DSC
HIGH IMPEDANCE
Figure 1. Converter Start Timing
HIGH
IMPEDANCE
CE
__
STS
DB11 – DB0
A
0
CS
R/C
_
t
HSR
t
SSR
t
HRR
t
SAR
t
HAR
t
DD
t
HL
HIGH
IMP.
DATA
VALID
t
HD
t
HS
t
SSR
Figure 2. Read Timing
V
CP
D
OUT
C
OUT
I
OH
I
OL
Figure 3. Load Circuit for Bus Timing Specifications
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