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參數(shù)資料
| 型號： | AD1818 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PCI SoundComm DC97 Digital Controller(PCI SoundComm DC97型數(shù)字控制器) |
| 中文描述： | 的PCI SoundComm DC97數(shù)字控制器（的PCI SoundComm DC97型數(shù)字控制器） |
| 文件頁數(shù)： | 19/29頁 |
| 文件大小： | 364K |
| 代理商： | AD1818 |
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AD1818
–19–
REV. 0
TECHNCAL
SYNC. This falling edge marks the time when both sides of the
AC Link are aware of the start of a new audio frame. On the
next rising of BIT_CLK, the AC ’97 controller transitions
SDATA_OUT into the first bit position of Slot 0 (valid frame
bit). Each new bit position is presented to the AC Link on a
rising edge of BIT_CLK, and subsequently sampled by the
AC ’97 on the following falling edge of BIT_CLK. This sequence
ensures that data transitions and subsequent sample points for
both incoming and outgoing data streams are time aligned.
SDATA_OUT’s composite stream is MSB justified (MSB first)
with all nonvalid slots’ bit positions stuffed with 0s by the
AD1818.
For all valid slots, the AD1818 provides 16 valid data bits and
stuffs 0s in the nonvalid trailing bit positions.
Slot 1: Command Address Port
The command port is used to control fractures, and monitor
status (see Audio Input Frame Slots 1 and 2) for AC ’97
functions including, but not limited to, mixer settings and
power management.
The control interface architecture supports up to 64 16-bit
read/write registers. Audio Output Frame Slot 1 stream
communicates control register address and write/read com-
mand information to the AC ’97.
DATA
ANALOG/DIGITAL INTERFACE
Analog/Digital AC ’97 Protocol
For complete information on AC ’97, please refer to the Analog
Devices’ AD1819 data sheet.
AC ’97 incorporates a 5-pin digital serial interface that links it to
the AD1818. AC Link is a bidirectional, fixed rate, serial PCM
digital stream. It handles multiple input and output audio
streams, as well as control register accesses employing a time
division multiplexed (TDM) scheme. The AC Link architecture
divides each audio frame into 12 outgoing and 12 incoming data
streams, each with 20-bit sample resolution. The AD1818
provides and accepts data with 16-bit resolution.
Synchronization of all AC Link data transactions is signaled by
the AD1818. The AC ’97 codec drives the serial bit clock onto
the AC Link, which the AD1818 then qualifies with a synchro-
nization signal to construct audio frames.
SYNC, fixed at 48 kHz, is derived by dividing down the serial
bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz,
provides the necessary clocking granularity to support 12, 20-bit
outgoing and incoming time slots. AC Link serial data is
transitioned on each rising edge of BIT_CLK. The receiver of
AC Link data, the AC ’97 codec for outgoing data and the
AD1818 for incoming data, samples each serial bit on the falling
edges of BIT_CLK.
The AC Link protocol provides for a special 16-bit time slot
(Slot 0) wherein each bit conveys a valid tag for its correspond-
ing time slot within the current audio frame. A “1” in a given bit
position of Slot 0 indicates that the corresponding time slot
within the current audio frame has been assigned to a data
stream and contains valid data. If a slot is “tagged,” it is the
responsibility of the source of the data for that slot (the AC ’97
codec for the input stream, digital controller for the output stream)
to stuff all bit positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the
beginning of each audio frame. The portion of the audio frame
where SYNC is high is defined as the “Tag Phase.” The
remainder of the audio frame where SYNC is low is defined as
the “Data Phase.”
Additionally, for power savings, all clock, sync and data signals
can be halted. This requires that the AC ’97 codec be imple-
mented as a static design to allow its register contents to remain
intact when entering a power savings mode.
AC Link Audio Output Stream (SDATA_OUT)
The audio output frame data streams correspond to the multi-
plexed bundles of all digital output data targeting the AC ’97’s
DAC inputs and control registers. As briefly mentioned earlier,
each audio frame supports up to twelve 20-bit outgoing data
time slots. Slot 0 is a special reserved time slot containing
16 bits used for AC Link protocol infrastructure.
Within Slot 0, the first bit is a global bit (SDATA_OUT Slot 0
Bit 15) that flags the validity of the entire audio frame. If the
“Valid Frame” bit is a 1, this indicates that the current audio
frame contains at least one slot time of valid data. The next
12-bit position sampled by the AC ’97 indicates which of the
corresponding 12 time slots contain valid data. In this way,
data streams of differing sample rates can be transmitted across
slot- based AC Link protocol.
A new audio output frame begins with a low to high transi-
rising edge of BIT_CLK. On the immediately following
falling edge of BIT_CLK, the AC ’97 samples the assertion of
TAG PHASE
DATA PHASE
20μs
(48kHz)
VALID
END OF PREVIOUS
AUDIO FRAME
TIME SLOT "VALID"
BITS
("1" = TIME SLOT CONTAINS VALID PCM DATA)
SLOT 1
SLOT 2
SLOT 3
SLOT 12
SLOT(2)
SLOT(12)
SLOT(1)
"0"
"0"
"0"
19
19
0
0
19
19
0
0
SYNC
BIT_CLK
SDATA_OUT
12.288MHz
81.4ns
Figure 8. Time-Slot-Based AC Link Protocol
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1819A | AC97 SoundPort Codec(AC97型聲音端口信號編解碼器) |
| AD1819BJST | AC’97 SoundPort Codec |
| AD1819 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1819B | AC’97 SoundPort Codec |
| AD1833A | 24-Bit, 192 kHz, DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD18-182 | 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Non-Insulated; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:DISCONNECTFEMALE 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 21.08mm 5.84mm Tin |
| AD18-183 | 制造商:Thomas & Betts 功能描述:Terminal; 22 to 18 AWG; Brass; Nylon; Tin Plated; UL 94V-2 制造商:Thomas & Betts 功能描述:NON-INS FEM-187 DISC, 22-18 LEN .64 制造商:Thomas & Betts 功能描述:Quick Disconnect Terminal 18-22AWG F 16.26mm 5.84mm Tin |
| AD1819 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec |
| AD1819AJST | 制造商:Rochester Electronics LLC 功能描述: |
| AD1819B | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC’97 SoundPort Codec |
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