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AD1819A
–18–
REV. 0
Sample Rate 0 (Index 78h)
g
m
u
e
R
N
e
m
a
N
5
1
D
4
1
D
3
1
D
2
1
D
1
1
D
0
1
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
t
a
D
h
8
7
0
e
R
e
m
a
S
5
1
0
R
S
4
1
0
R
S
3
1
0
R
S
2
1
0
R
S
1
1
0
R
S
0
1
0
R
S
9
0
R
S
8
0
R
S
7
0
R
S
6
0
R
S
5
0
R
S
4
0
R
S
3
0
R
S
2
0
R
S
1
0
R
S
0
0
R
S
h
0
8
B
B
SR0 [15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
g
m
u
e
R
N
e
m
a
N
5
1
D
4
1
D
3
1
D
2
1
D
1
1
D
0
1
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
t
a
D
h
A
7
1
e
R
e
m
a
S
5
1
1
R
S
4
1
1
R
S
3
1
1
R
S
2
1
1
R
S
1
1
1
R
S
0
1
1
R
S
9
1
R
S
8
1
R
S
7
1
R
S
6
1
R
S
5
1
R
S
4
1
R
S
3
1
R
S
2
1
R
S
1
1
R
S
0
1
R
S
h
0
8
B
B
SR1 [15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hz increments. T he sample rate may be multiplied by 8/7 or 10/7 by setting Bits D6 and D5 in Register 76h.
Vendor ID (Index 7Ch–7E h)
g
m
u
e
R
N
e
m
a
N
5
1
D
4
1
D
3
1
D
2
1
D
1
1
D
0
1
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
t
a
D
h
C
7
1
D
I
r
o
d
n
e
V
7
F
6
F
5
F
4
F
3
F
2
F
1
F
0
F
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
S
h
4
4
1
4
S [7:0]
F [7:0]
T his register is ASCII encoded to “A.”
T his register is ASCII encoded to “D.”
g
m
u
e
R
N
e
m
a
N
5
1
D
4
1
D
3
1
D
2
1
D
1
1
D
0
1
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
t
a
D
h
E
7
2
D
I
r
o
d
n
e
V
7
T
6
T
5
T
4
T
3
T
2
T
1
T
0
T
7
V
E
R
6
V
E
R
5
V
E
R
4
V
E
R
3
V
E
R
2
V
E
R
1
V
E
R
0
V
E
R
h
3
0
3
5
T [7:0]
REV [7:0]
T his register is ASCII encoded to “S.”
Revision Register field contains the revision number.
T hese bits are read-only and should be verified before accessing vendor-defined features.
DIGIT AL INT E RFACE
AD1819A AC-Link Digital Serial Interface Protocol
T he AD1819A incorporates an AC ’97 5-pin digital serial interface that links it to a digital controller. AC-Link is a bidirectional,
fixed rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employ-
ing a time division multiplexed (T DM) scheme. T he AC-Link architecture divides each audio frame into 12 outgoing and 12 incom-
ing data streams, up to 20-bit sample resolution. T he AD1819A uses 16-bit samples. T he data streams include:
AC ’97 Protocol
T AG
1 Input and Output
Control
2 Output Slots
Control Register Write Port
Status
2 Input Slots
Control Register Read Port
PCM Playback
2 Output Slots
2-Channel Composite PCM Output Stream
PCM Record Data
2 Input Slots
2-Channel Composite PCM Input Stream
Synchronization of all AC-Link data transactions is signaled by the AC ’97 controller. T he AD1819A drives the serial bit clock onto
AC-Link, which the AC ’97 controller then qualifies with a synchronization signal to construct audio frames.
SY NC, which is fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT _CL K ) by 256. T he BIT _CL K is fixed at
12.288 MHz. AC-Link serial data is updated on each rising edge of BIT _CLK . T he receiver of AC-Link data, the AD1819A for outgo-
ing data and the AC ’97 controller for incoming data, samples each serial bit on the falling edge of BIT _CLK . SYNC must remain
high for a minimum of 1 BIT _CLK up to a maximum duration of 16 BIT _CLK s at the beginning of each audio frame. T he first 16
bits of the audio frame is defined as the “T ag Phase.” T he remainder of the audio frame is the “Data Phase.” T he AD1819A uses
SYNC to define the beginning of the audio frame.