參數(shù)資料
型號(hào): AD1819B
廠商: Analog Devices, Inc.
元件分類: Codec
英文描述: AC’97 SoundPort Codec
中文描述: AC\u0026#39;97音效SoundPort編解碼器
文件頁數(shù): 7/28頁
文件大?。?/td> 245K
代理商: AD1819B
AD1819B
–7–
REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1819B features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Parameter
Power Supplies
Analog (AV
DD
)
Digital (DV
DD
)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
Storage Temperature
Min
Max
Units
–0.3
–0.3
6.0
6.0
±
10.0
AV
DD
+ 0.3 V
DV
DD
+ 0.3 V
+85
+150
V
V
mA
–0.3
–0.3
–40
–65
°
C
°
C
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option*
Model
AD1819BJST –40
°
C to +85
°
C 48-Terminal LQFP ST-48
*ST = Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
T
AMB
= T
CASE
– (P
D
× θ
CA
)
T
CASE
= Case Temperature in
°
C
P
D
= Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Package
u
JA
76.2
°
C/W
u
JC
17
°
C/W
u
CA
59.2
°
C/W
LQFP
BIT_CLK
SYNC
t
HOLD
SDATA_OUT
t
SETUP
Figure 4. Data Setup and Hold
BIT_CLK
SYNC
SDATA_IN
t
RISECLK
t
RISESYNC
t
RISEDIN
t
RISEDOUT
t
FALLCLK
t
FALLSYNC
t
FALLDIN
t
FALLDOUT
SDATA_OUT
Figure 5. Signal Rise and Fall Time
BIT_CLK
SDATA_OUT
SYNC
SDATA_IN
SLOT 1
SLOT 2
WRITE
PR4
CARE
t
S2_PDOWN
NOTE: BIT_CLK NOT TO SCALE
Figure 6. AC-Link, Link Low Power Mode Timing
RESET
SDATA_OUT
HI-Z
t
SETUP2RST
t
OFF
SDATA_IN, BIT_CLK
Figure 7. ATE Test Mode
WARNING!
ESD SENSITIVE DEVICE
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