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參數(shù)資料
| 型號： | AD1833 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Multichannel 24-Bit, 192 kHz, DAC |
| 中文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 419K |
| 代理商： | AD1833 |
REV. 0
AD1833
–13–
AUX-Mode Timing—Interfacing to a SHARC
In AUX mode, the AD1833 is the master and generates a frame
sync signal (FSTDM) on its L/
R
CLK pin, and a bit clock
(BCLKTDM) on its BCLK pin, both of which are used to
control the data transmission from the SHARC. The bit clock
runs at a frequency of 256
×
f
S.
In this mode all data is writ-
ten on the rising edge of the bit clock and read on the falling
edge of the bit clock. The AD1833 starts the frame by raising
a frame sync on the rising edge of bit clock. The SHARC recog-
nizes this on the following falling edge of bit clock, and is
ready to start outputting data on the next rising edge of bit
clock. Each channel is given a 32-bit clock slot, the data is left
justified and uses 16, 20, or 24 of the 32 bits. An enlarged dia-
gram (see Figure 6) is provided detailing this. The data is sent
from the SHARC to the AD1833 on the SDIN1 pin and is
provided in the following order, MSB first—Internal DACL0,
Internal DACL1, Internal DACL2, AUX DACL0, Internal
DACR0, Internal DACR1, Internal DACR2 and AUX DACR0.
The data is written on the rising edge of bit clock and read by
the AD1833 on the falling edge of bit clock. The left and right
data destined for the auxiliary DAC is sent to it in standard
I
2
S format in the next frame using the SDIN2, SDIN3, and
SOUT pins as the L/
R
CLK, BCLK, and SDIN pins respec-
tively for communicating with the auxiliary DAC.
DSP Mode Timing
DSP Mode Timing uses the rising edge of the frame sync
signal on the L/
R
CLK pin to denote the start of the transmis-
sion of a data word. Note that for both left and right channels a
rising edge is used; therefore in this mode there is no way to
determine which data is intended for the left channel and which is
intended for the right. The DSP writes data on the rising edge
of BCLK and the AD1833 reads it on the falling edge. The DSP
raises the frame sync signal on the rising edge of BCLK and
then proceeds to transmit data, MSB first, on the next rising
edge of BCLK. The data length can be 16, 20, or 24 bits. The
frame sync signal can be brought low any time at or after the
MSB is transmitted, but must be brought low at least one BCLK
period before the start of the next channel transmission.
INTERNAL
DAC L0
INTERNAL
DAC L1
INTERNAL
DAC L2
AUXILIARY
DAC L0
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUXILIARY
DAC R0
FSTDM
BCLKTDM
MSB
24-BIT DATA
20-BIT DATA
16-BIT DATA
BCLKTDM
–
1
–
2
–
3
–
4
+8
+7
+6
+5
+4
+3
+2
+1
LSB
MSB
–
1
–
2
–
3
–
4
+4
+3
+2
+1
LSB
MSB
–
1
–
2
–
3
–
4
LSB
Figure 7. Aux-Mode Timing
L/
R
CLK
BCLK
SDATA
MSB
–
1
–
2
–
3
–
4
–
5
–
6
MSB
–
1
–
2
–
3
–
4
–
5
–
6
MSB
32 BCLKs
32 BCLKs
Figure 8. DSP Mode Timing
SHARC is a registered trademark of Analog Devices, Inc.
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| AD1833AASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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