參數(shù)資料
型號(hào): AD1933WBSTZ
廠商: Analog Devices Inc
文件頁數(shù): 7/28頁
文件大?。?/td> 0K
描述: IC DAC 24BIT SRL/SPI 64LQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 429mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
輸出數(shù)目和類型: 8 電壓,雙極
采樣率(每秒): *
Data Sheet
AD1933
Rev. E | Page 15 of 28
DAISY-CHAIN MODE
The AD1933 also allows a daisy-chain configuration to expand
the system 16 DACs (see Figure 12). In this mode, the DBCLK
frequency is 512 fS. The first eight slots of the DAC TDM data
stream belong to the first AD1933 in the chain and the last eight
slots belong to the second AD1933. The second AD1933 is the
device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1933 can be configured into a dual-line, DAC TDM mode,
as shown in Figure 13. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1933 in the chain and the last four channels belong to
the second AD1933.
The dual-line, DAC TDM mode can also be used to send data at
a 192 kHz sample rate into the AD1933, as shown in Figure 14.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 12 for a detailed description of
the function of each pin. See Figure 18 for a typical AD1933
configuration with two external stereo DACs. Figure 15 and
Figure 16 show the serial mode formats. For maximum
flexibility, the polarity of LRCLK and BCLK are programmable.
In these figures, all of the clocks are shown with their normal
polarity. The default mode is I2S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1933
DSDATA2 (TDM_OUT)
OF THE SECOND AD1933
THIS IS THE TDM
TO THE FIRST AD1933
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
32 BITS
DSP
SECOND
AD1933
FIRST
AD1933
06
624
-01
2
Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1933 Daisy Chain)
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1
DAC R1
DAC L2
DAC R2
DAC L1
DAC R1
DAC L2
DAC R2
DSDATA3
(IN)
DAC L3
DAC R3
DAC L4
DAC R4
DAC L3
DAC R3
DAC L4
DAC R4
DSDATA2
(OUT)
DAC L1
DAC R1
DAC L2
DAC R2
DSDATA4
(OUT)
DAC L3
DAC R3
DAC L4
DAC R4
32 BITS
DSP
SECOND
AD1933
FIRST
AD1933
MSB
06
62
4-
01
3
Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1933 Daisy Chain; DSDATA3 and DSDATA4 Are the Daisy Chain)
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