參數(shù)資料
型號(hào)： AD1937WBSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/36頁
文件大?。?/td> 0K
描述： IC CODEC 4/ADC DIFF OUT 64-LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 通用
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 4 / 8
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 96 / 96
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 105 / 110
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁面： 776 (CN2011-ZH PDF)
AD1937
Rev. B | Page 19 of 36
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
The ADC and DAC serial data modes default to I2S stereo.
The ports can also be programmed for left-justified stereo,
right-justified stereo, and TDM modes. The word width is
24 bits by default and can be set to 16 or 20 bits in the DAC
Control 2 and ADC Control 1 registers. The DAC serial formats
are programmable in the DAC Control 0 register. The polarity of
DBCLK and DLRCLK is programmable in the DAC Control 1 reg-
ister. The ADC serial format is programmable in ADC Control 1
register. The ABCLK and ALRCLK clock polarities are pro-
grammed in ADC Control 2 register. In Figure 2, Figure 3, and
Figure 15 all of the clocks are shown with their normal polarity.
Both DAC and ADC serial ports can be programmed to become
the bus masters according to DAC Control 1 and ADC Control 2
registers. By default, both ADC and DAC serial ports are in the
slave mode.
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDATA
LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB
1/
fS
0
74
14-
02
4
Figure 15. Stereo Modes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1937WBSTZ-RL 功能描述:IC CODEC 4/ADC DIFF OUT 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
AD1937XSTZ 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
AD1937XSTZRL 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
AD1938 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC
AD1938WBSTZ 功能描述:IC CODEC 24BIT 4ADC/8DAC 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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