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參數(shù)資料
| 型號： | AD1939YSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC 24BIT ADC/DAC 64LQFP |
| 標準包裝： | 1 |
| 類型： | 通用 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 4 / 8 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標準 ADC / DAC (db)： | 94 / 94 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 105 / 110 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD1939
Data Sheet
Rev. E | Page 14 of 32
master clock. In addition, it is especially important that the
clock signal not pass through an FPGA, CPLD, or other large
digital chip (such as a DSP) before being applied to the
AD1939. In most cases, this induces clock jitter due to the
sharing of common power and ground connections with other
unrelated digital output signals. When the PLL is used, jitter in
the reference clock is attenuated above a certain frequency
depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to their
default settings. To avoid pops, reset does not power down the
analog outputs. After RST is deasserted and the PLL acquires
lock condition, an initialization routine runs inside the
AD1939. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. To
guarantee proper startup, the RST pin should be pulled low by
an external resistor.
SERIAL CONTROL PORT
The AD1939 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. A standalone mode is also available
for operation without serial control; standalone is configured at
reset by connecting CIN, CCLK, and CLATCH to ground. In
standalone mode, all registers are set to default, except the
internal MCLK enable, which is set to 1. The ADC, ABCLK, and
ALRCLK clock ports are set to master/slave by the connecting
the COUT pin to either DVDD or ground. Standalone mode
only supports stereo mode with an I2S data format and 256 fS
MCLK rate. Refer to Table 11 for details. If CIN, CCLK, and
CLATCH are not grounded, the AD1939 SPI port is active. It is
recommended to use a weak pull-up resistor on CLATCHin
applications that have a microcontroller. This pull-up resistor
ensures that the AD1939 recognizes the presence of a
microcontroller.
The SPI control port of the AD1939 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1939, the address is 0x04, shifted left one bit due to the R/W
bit. The second byte is the AD1939 register address and the
third byte is the data.
Table 11. Standalone Mode Selection
ADC Clocks
CIN
COUT
CCLK
CLATCH
Slave
0
Master
0
1
0
D0
D8
D22
D23
D9
CLATCH
CCLK
CIN
COUT
tCCH tCCL
tCDS tCDH
tCLS
tCCP
tCLH
tCOTS
tCOD
tCOE
06
07
1-
0
10
Figure 11. Format of the SPI Signal
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| AD1939YSTZRL | 功能描述:IC CODEC 24BIT ADC/DAC 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| AD1940 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP-TM Multichannel 28-Bit Audio Processor |
| AD1940YST | 制造商:Analog Devices 功能描述:Audio Processor 48-Pin LQFP |
| AD1940YSTRL | 制造商:Analog Devices 功能描述:Audio Processor 48-Pin LQFP T/R |
| AD1940YSTZ | 功能描述:IC DSP AUDIO 16CH/28BIT 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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