參數(shù)資料
型號(hào): AD1939YSTZRL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/32頁(yè)
文件大?。?/td> 0K
描述: IC CODEC 24BIT ADC/DAC 64-LQFP
標(biāo)準(zhǔn)包裝: 1,500
類型: 通用
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 4 / 8
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 94 / 94
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 105 / 110
電壓 - 電源,模擬: 3 V ~ 3.6 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 帶卷 (TR)
Data Sheet
AD1939
Rev. E | Page 25 of 32
Table 17. PLL and Clock Control 1 Register
Bit
Value
Function
Description
0
PLL clock
DAC clock source select
1
MCLK
1
0
PLL clock
ADC clock source select
1
MCLK
2
0
Enabled
On-chip voltage reference
1
Disabled
3
0
Not locked
PLL lock indicator (read only)
1
Locked
7:4
0000
Reserved
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
Bit
Value
Function
Description
0
Normal
Power-down
1
Power-down
2:1
00
32 kHz/44.1 kHz/48 kHz
Sample rate
01
64 kHz/88.2 kHz/96 kHz
10
128 kHz/176.4 kHz/192 kHz
11
Reserved
5:3
000
1
SDATA delay (BCLK periods)
001
0
010
8
011
12
100
16
101
Reserved
110
Reserved
111
Reserved
7:6
00
Stereo (normal)
Serial format
01
TDM (daisy chain)
10
DAC AUX mode (ADC-, DAC-, TDM-coupled)
11
Dual-line TDM
Table 19. DAC Control 1 Register
Bit
Value
Function
Description
0
Latch in mid cycle (normal)
BCLK active edge (TDM in)
1
Latch in at end of cycle (pipeline)
2:1
00
64 (2 channels)
BCLKs per frame
01
128 (4 channels)
10
256 (8 channels)
11
512 (16 channels)
3
0
Left low
LRCLK polarity
1
Left high
4
0
Slave
LRCLK master/slave
1
Master
5
0
Slave
BCLK master/slave
1
Master
6
0
DBCLK pin
BCLK source
1
Internally generated
7
0
Normal
BCLK polarity
1
Inverted
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