參數資料
型號: AD1991
廠商: Analog Devices, Inc.
英文描述: Class D/1-Bit Audio Power Output Stage
中文描述: D/1-Bit類音頻功率輸出級
文件頁數: 5/11頁
文件大小: 194K
代理商: AD1991
REV. 0
AD1991
–5–
PIN CONFIGURATION
52 51 50 49 48
43 42 41 40
47 46 45 44
14 15 16 17 18 19 20 21 22 23 24 25 26
D
D
1
2
3
4
5
6
7
8
9
10
11
13
12
PIN 1
(TOP VIEW
39
38
37
36
35
34
33
32
31
30
29
28
27
AD1991
P
PGND1
OUTA
OUTA
OUTA
PV
DD1
PV
DD1
PV
DD1
PGND1
PGND1
PGND1
PGND2
OUTC
OUTC
OUTC
PV
DD2
PV
DD2
PV
DD2
PGND2
PGND2
PGND2
OUTB
OUTB
OUTB
OUTD
OUTD
OUTD
P
P
A
A
A
A
P
P
P
M
M
A
D
D
E
E
E
E
I
I
M
R
/
P
C
I
I
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic In/Out
Description
1
2, 3, 4
5, 6, 7
8, 9, 10
11, 12, 13
14
PGND1
OUTA
PV
DD1
OUTB
PGND1
ERR3
Negative power supply for high power Transistors A2 and B2.
Output of transistor pair A1 and A2.
Positive power supply for high power Transistors A1 and B1.
Output of transistor pair B1 and B2.
Negative power supply for high power Transistors A2 and B2.
Edge speed setting MSB during RESET/active low thermal shutdown error output during
normal operation.
Edge speed setting Bit 1 during RESET/active low thermal warning error output during
normal operation.
Nonoverlap time setting MSB during RESET/active thermal low shutdown error output
during normal operation.
Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side
transistor disable input during normal operation.
Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode.
Edge speed setting LSB during RESET/during normal operation, control pin for Transistors
B1 and B2 in 4-channel mode; no function in 2-channel mode.
Positive power supply for low power digital circuitry.
Negative power supply for low power digital circuitry.
Active low clickless mute input.
Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode.
Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis-
tors D1 and D2 in 4-channel mode; no function in 2-channel mode.
Active low RESET/power-down input.
External clock input in external clock mode.
Negative power supply for high power Transistors C2 and D2.
Output of transistor pair D1 and D2.
Positive power supply for high power Transistors C1 and D1.
Output of transistor pair C1 and C2.
Negative power supply for high power Transistors C2 and D2.
Negative power supply for low power analog circuitry.
Clock source select (referenced to AGND); normally connected to AGND.
Positive power supply for low power analog circuitry.
Channel mode select (referenced to AGND).
Negative power supply for high power Transistors A2 and B2.
O
O
I/O
15
ERR2
I/O
16
ERR1
I/O
17
ERR0
I/O
18
19
INA
INB
I
I
20
21
22
23
24
DV
DD
DGND
MUTE
INC
IND
I
I
I
25
26
27, 28, 29
30, 31, 32
33, 34, 35
36, 37, 38
39, 40, 41, 42
43, 45, 48, 49
44
46
47
50, 51, 52
RST
/
PDN
CLK
PGND2
OUTD
PV
DD2
OUTC
PGND2
AGND
MODE0
AV
DD
MODE1
PGND1
I
I
O
O
I
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