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參數(shù)資料
| 型號： | AD202KY |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP ISOL 2KHZ DUAL LP 38DIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 隔離 |
| 電路數(shù)： | 2 |
| 增益帶寬積： | 2kHz |
| 電流 - 輸入偏壓： | 30pA |
| 電壓 - 輸入偏移： | 5000µV |
| 電流 - 電源： | 5mA |
| 電流 - 輸出 / 通道： | 400µA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 38-SIP，10 引線，偏移引線 |
| 供應(yīng)商設(shè)備封裝： | 10-SIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 772 (CN2011-ZH PDF) |
REV. D
AD202/AD204
–5–
AD246 Clock Driver. The AD246 is a compact, inexpensive
clock driver that can be used to obtain the required clock from a
single 15 V supply. Alternatively, the circuit shown in Figure 4
(essentially an AD246) can be used. In either case, one clock
circuit can operate at least 32 AD204s at the rated minimum
supply voltage of 14.25 V and one additional isolator can be
operated for each 40 mV increase in supply voltage up to 15 V.
A supply bypass capacitor is included in the AD246, but if many
AD204s are operated from a single AD246, an external bypass
capacitor should be used with a value of at least 1
mF for every
five isolators used. Place the capacitor as close as possible to the
clock driver.
180pF
49.9k
C
RC
R
2
3
1
Q
CD
4047B
14
6
5
12 9
8
74
10
2
4
TELEDYNE
TSC426
3
1N914
6
7
5
+ 1 F
35V
15V
CLK
OUT
CLK AND
PWR COM
Figure 4. Clock Driver
Input Configurations. The AD202 and AD204 have been
designed to be very easy to use in a wide range of applications.
The basic connection for standard unity gain applications, useful
for signals up to
±5 V, is shown in Figure 5; some of the possible
variations are described below. When smaller signals must be
handled, Figure 6 shows how to achieve gain while preserving a
very high input resistance. The value of feedback resistor RF
should be kept above 20 k
W for best results. Whenever a gain of
more than five is taken, a 100 pF capacitor from FB to IN COM
is required. At lower gains this capacitor is unnecessary, but it
will not adversely affect performance if used.
OUT
HI
OUT
LO
IN–
IN+
IN COM
15V OR
CLOCK
AD202
OR
AD204
VOUT
5V
2k
(SEE TEXT)
VSIG
( 5V)
FB
Figure 5. Basic Unity-Gain Application
AD202
OR
AD204
2k
VSIG
VO
VO = VSIG
1 + –––
RF 20k
RF
RG
RF
RG
100pF
(
)
Figure 6. Input Connections for Gain > 1
The noninverting circuit of Figures 5 and 6 can also be used to
your advantage when a signal inversion is needed: just interchange
either the input leads or the output leads to get inversion. This
approach retains the high input resistance of the noninverting
circuit, and at unity gain no gain-setting resistors are needed.
When the isolator is not powered, a negative input voltage of
more than about 2 V will cause an input current to flow. If the
signal source can supply more than a few mA under such con-
ditions, the 2 k
W resistor shown in series with IN+ should be
used to limit current to a safe value. This is particularly impor-
tant with the AD202, which may not start if a large input current
is present.
Figure 7 shows how to accommodate current inputs or sum
currents or voltages. This circuit can also be used when the
input signal is larger than the
±5 V input range of the isolator;
for example, a
±50 V input span can be accommodated with
RF = 20 k
W and RS = 200 kW. Once again, a capacitor from FB
to IN COM is required for gains above five.
AD202
OR
AD204
RS2
V
V = –
(V
S1 ––– + V S2 ––– + IS RF + ...
)
RF 20k
RF
RS1
RF
RS2
RF
RS1
IS
VS1
VS2
Figure 7. Connections for Summing or Current Inputs
(NOTE: Circuit figures shown on this page are for SIP-style packages. Refer to
Page 3 for proper DIP package pinout.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD202KY | 制造商:Analog Devices 功能描述:IC AMP ISOLATION |
| AD-2031 | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:ADSL LINE TRANSFORMER |
| AD-2032S | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:ADSL LINE TRANSFORMER |
| AD-2037S | 制造商:BOTHHAND 制造商全稱:Bothhand USA, LP. 功能描述:ADSL LINE TRANSFORMER |
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