參數(shù)資料
型號(hào)： AD5060ARJZ-2REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/24頁(yè)
文件大小： 0K
描述： IC DAC 16BIT SPI/SRL SOT23-8
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： nanoDAC™
設(shè)置時(shí)間： 4µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 6mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8
供應(yīng)商設(shè)備封裝： SOT-23-8
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 250k
其它名稱： AD5060ARJZ-2REEL7DKR
AD5040/AD5060
Rev. A | Page 16 of 24
The AD5040 input shift register is 16 bits wide; see Figure 42.
PD1 and PD0 are control bits that control the operating mode
of the part—normal mode or any one of two power-down
modes (see Power-Down Modes section for more detail). The
next 14 bits are the data bits. These are transferred to the DAC
register on the 16th falling edge of SCLK.
SYNC Interrupt
In a normal write sequence for the AD5060, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, the write sequence is
interrupted. The shift register is reset and the write sequence is
considered invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs; see
. In a normal write sequence for the AD5040, the
SYNC line
is kept low for at least 16 falling edges of SCLK, and the DAC is
updated on the 16th falling edge. However, if SYNC is brought
high before the 16th falling edge, the write sequence is
interrupted. The shift register is reset and the write sequence is
considered invalid. Neither an update of the DAC register
contents nor a change in the operating mode occurs.
POWER-ON RESET
The AD5040 and AD5060 both contain a power-on reset
circuit that controls the output voltage during power-up. The
DAC register is filled with the zero-scale code or midscale code
and the output voltage is set to zero scale or midscale (see the
Ordering Guide for more details on the reset model). It remains
there until a valid write sequence is made to the DAC. This is
useful in applications where it is important to know the output
state of the DAC while it is in the process of powering up.
SOFTWARE RESET
The AD5060 device can be put into software reset by setting all
bits in the DAC register to 1; this includes writing 1s to Bit D23
and Bit D16, which is not the normal mode of operation. For
the AD5040 this includes writing 1s to Bit D15 and Bit D14,
which is also not the normal mode of operation. Note that the
SYNC interrupt command cannot be performed if a software
reset command is started in the AD5040 or AD5060.
04767-074
DATA BITS
DB13 (MSB)
DB0 (LSB)
D13
PD0
PD1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL OPERATION
100k
Ω TO GND
3-STATE
POWER-DOWN MODES
0
1
0
1
0
Figure 42. AD5040 Input Register Content
04767
-031
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
SYNC
SCLK
DIN
Figure 43. AD5060 SYNC Interrupt Facility
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