- 您現(xiàn)在的位置：買賣IC網 > PDF目錄8689 > AD5061BRJZ-1500RL7 (Analog Devices Inc)IC DAC 16BIT SPI/SRL SOT23-8 PDF資料下載
參數(shù)資料
| 型號： | AD5061BRJZ-1500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SPI/SRL SOT23-8 |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 500 |
| 系列： | nanoDAC™ |
| 設置時間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 6mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 1.3M |
AD5061
Rev. B | Page 16 of 20
POWER-ON TO ZERO-SCALE OR MIDSCALE
The AD5061 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the zero-scale or midscale code and the output voltage is zero-
scale or midscale. It remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bit D23 to
Bit D16, which is not the normal mode of operation. Note that
the SYNC interrupt command cannot be performed if a
software reset command is started.
POWER-DOWN MODES
The AD5061 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation
DB17
DB16
Operating Mode
0
Normal operation
Power-down mode:
0
1
3-state
1
0
100 kΩ to GND
1
1 kΩ to GND
When both bits are set to 0, the part works normally with its
normal power consumption. However, for the three power-
down modes, the supply current falls to less than 1 μA at 5 V
(265 nA at 3 V). Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a
1 kΩ resistor or a 100 kΩ resistor, or it is left open-circuited
(3-state). The output stage is illustrated in Figure 39.
POWER-DOWN
CIRCUITRY
AD5061
DAC
04
76
2-
02
9
VOUT
RESISTOR
NETWORK
OUTPUT
BUFFER
Figure 39. Output Stage During Power-Down
The bias generator, the DAC core and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V;
see Figure 19.
MICROPROCESSOR INTERFACING
AD5061-to-ADSP-2101/ADSP-2103 Interface
Figure 40 shows a serial interface between the AD5061 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
AD5061
1ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
DIN
SCLK
04
76
2-
0
30
ADSP-2101/
ADSP-21031
Figure 40. AD5061-to-ADSP-2101/ADSP-2103 Interface
0
476
2-
0
31
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
SYNC
SCLK
DIN
Figure 41. SYNC Interrupt Facility
相關PDF資料 |
PDF描述 |
|---|---|
| V48A12H500BF | CONVERTER MOD DC/DC 12V 500W |
| AD5336BRUZ-REEL7 | IC DAC 10BIT QUAD VOUT 28-TSSOP |
| V48A12H500BL3 | CONVERTER MOD DC/DC 12V 500W |
| V48A12H500BL | CONVERTER MOD DC/DC 12V 500W |
| PI49FCT3807DHE | IC CLK BUFF 1:10 156MHZ 20-SSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD5061BRJZ-1REEL7 | 功能描述:IC DAC 16BIT SPI/SRL SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:nanoDAC™ 產品培訓模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5061BRJZ-2 | 制造商:Analog Devices 功能描述:DAC SGL R-2R 16BIT 8PIN SOT-23 - Bulk |
| AD5061BRJZ-2500RL7 | 功能描述:IC DAC 16BIT SPI/SRL SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:nanoDAC™ 產品培訓模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應商設備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5061BRJZ-2REEL7 | 功能描述:IC DAC 16BIT SPI/SRL SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:nanoDAC™ 產品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:3,000 系列:nanoDAC™ 設置時間:80µs 位數(shù):18 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應商設備封裝:SOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極 采樣率（每秒）:- 產品目錄頁面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名稱:AD5680BRJZ-2REEL7TR |
| AD5061BRJZ-3 | 制造商:Analog Devices 功能描述:DAC SGL R-2R 16BIT 8PIN SOT-23 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。