- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8980 > AD5062BRJZ-1500RL7 (Analog Devices Inc)IC DAC 16BIT 2.7-5.5V SOT23-8 PDF資料下載
參數(shù)資料
| 型號(hào)： | AD5062BRJZ-1500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V SOT23-8 |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 1.3M |
| 其它名稱： | AD5062BRJZ-1500RL7DKR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)
AD5062
Rev. A | Page 15 of 20
POWER-ON TO MIDSCALE OR ZERO SCALE
The AD5062 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the midscale code and the output voltage is midscale or the
DAC register is filled with the zero-scale code and the output
voltage is zero-scale. It remains there until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bit D23 to
Bit D16, which is not the normal mode of operation. Note that
the SYNCinterrupt command cannot be performed if a soft-
ware reset command is started.
POWER-DOWN MODES
The AD5062 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation for the AD5062
DB17
DB16
Operating Mode
0
Normal operation
Power-down mode:
0
1
3-state
1
0
100 kΩ to GND
1
1 kΩ to GND
When both bits are set to 0, the part works normally with its
normal power consumption. However, for the three power-
down modes, the supply current falls to less than 1 μA at 5.5 V.
Not only does the supply current fall, but the output stage is
also internally switched from the output of the DAC to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options. The
output is connected internally to GND through a 1 kΩ resistor
or a 100 kΩ resistor, or it is left open-circuited (3-state). The
output stage is illustrated in Figure 35.
POWER-DOWN
CIRCUITRY
AD5062
DAC
04766-029
VOUT
RESISTOR
NETWORK
Figure 35. Output Stage During Power-Down
The bias generator, the DAC core, and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are unaf-
fected when in power-down. The time to exit power-down is
MICROPROCESSOR INTERFACING
AD5062 to ADSP-2101/ADSP-2103 Interface
Figure 36 shows a serial interface between the AD5062 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
AD5062
1ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
DIN
SCLK
04766-030
ADSP-2101/
ADSP-21031
Figure 36. AD5062 to ADSP-2101/ADSP-2103 Interface
04766-031
DB23
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
SYNC
SCLK
DIN
Figure 37. SYNC Interrupt Facility
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B0Z-MY-F2 | CONVERTER MOD DC/DC 2V 20W |
| 206306-5 | CONN RCPT CPC 37POS PANEL MOUNT |
| VI-B0Z-MY-F1 | CONVERTER MOD DC/DC 2V 20W |
| VI-B0Z-MX-F4 | CONVERTER MOD DC/DC 2V 30W |
| VI-B0Z-MX-F3 | CONVERTER MOD DC/DC 2V 30W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5062BRJZ-1REEL7 | 功能描述:IC DAC 16BIT 2.7-5.5V SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5062BRJZ-2 | 制造商:Analog Devices 功能描述:DAC 1CH R-2R 16BIT 8PIN SOT-23 - Bulk |
| AD5062BRJZ-2500RL7 | 功能描述:IC DAC 16BIT 2.7-5.5V SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD5062BRJZ-2REEL7 | 功能描述:IC DAC 16BIT 2.7-5.5V SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5063 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Full Accurate 14/16 Bit Vout nanoDac Buffered, 3V/5V, Sot 23 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。