參數(shù)資料
型號： AD5064BRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 12/28頁
文件大?。?/td> 0K
描述： IC DAC 16BIT 4CH BUF OUT 16TSSOP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1,000
系列： nanoDAC™
設置時間： 8µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 30mW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電壓，雙極
采樣率（每秒）： 125k
AD5024/AD5044/AD5064
Data Sheet
Rev. F | Page 2 of 28
TABLE OF CONTENTS
REVISION HISTORY
6/13—Rev. E to Rev. F
Change to Standalone Mode Section........................................... 21
5/11—Rev. D to Rev. E
Changes to Table 4............................................................................ 5
Changes to Figure 4 and Figure 5................................................... 6
8/10—Rev. C to Rev. D
Change to Minimum SYNC High Time (Single Channel
Update) Parameter, Table 4 ............................................................. 5
5/10—Rev. B to Rev. C
Changes to Power-On Reset Section............................................ 22
6/09—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
3/09—Rev. 0 to Rev. A
Added 14-Lead TSSOP ......................................................Universal
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Features Section, General Description Section,
Product Highlights Section, Figure 2, and Table 1....................... 1
Changes to Table 2............................................................................ 3
Changes to Timing Characteristics Section and Table 4............. 5
Added Circuit and Timing Diagrams Section and Figure 3....... 5
Added Figure 5...................................................................................6
Changes to Figure 4...........................................................................6
Added Figure 6...................................................................................8
Added Table 6; Renumbered Sequentially .....................................8
Changed Input Shift Register to Shift Register Throughout .......8
Changes to Table 7.............................................................................9
Changes to Typical Performance Characteristics Section ........ 10
Changes to Terminology Section ................................................. 17
Changes to Digital-to-Analog Converter Section, Reference
Buffer Section, Output Amplifier Section, Serial Interface
Section, Shift Register Section, and Table 8................................ 19
Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20
Added Modes of Operation Section, Daisy-Chaining Section,
Table 10, and Table 11.................................................................... 21
Changes to Table 13 and Power-Down Mode Section .............. 22
Changes to Table 16 ....................................................................... 24
Changes to Figure 52 to Figure 55................................................ 25
Changes to Bipolar Operation Section and Figure 56 to
Figure 58 .......................................................................................... 26
Added Figure 59 ............................................................................. 27
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
8/08—Revision 0: Initial Version
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