參數(shù)資料
型號(hào)： AD5066ARUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT 2.7-5.5V 16TSSOP
標(biāo)準(zhǔn)包裝： 1
系列： nanoDAC™
設(shè)置時(shí)間： 15µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，雙極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 781 (CN2011-ZH PDF)
AD5066
Rev. A | Page 15 of 24
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5066 is a quad 16-bit, serial input, voltage output
nanoDAC. The part operates from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5066 in a 32-bit word format via
a 3-wire serial interface. The AD5066 incorporates a power-on
reset circuit to ensure the DAC output powers up to a known
output state. The devices also have a software power-down mode
that reduces the typical current consumption to typically 400 nA.
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
N
REFIN
OUT
D
V
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5066 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 39. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either GND or the VREF
buffer
output. The remaining 12 bits of the data word drive the S0 to
S11 switches of a 12-bit voltage mode R-2R ladder network.
2R
S0
VREF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
VOUT
12-BIT R-2R LADDER
FOUR MSBs DECODED
INTO 15 EQUAL
SEGMENTS
06
84
5-
00
5
Figure 39. DAC Ladder Structure
REFERENCE BUFFER
The AD5066 operates with an external reference. Each of the
four on-board DACs has a dedicated voltage reference pin that
is buffered. The reference input pin has an input range of 2 V
to VDD 0.4 V. This input voltage is then used to provide a
buffered reference for the DAC core.
SERIAL INTERFACE
The AD5066 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. See Figure 2 for a timing diagram
of a typical write sequence.
INPUT SHIFT REGISTER
The input shift register is 32 bits wide (see Figure 40). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 8), and finally the bit data-word. The
data-word comprises of a 16-bit input code followed by four don’t
care bits (see Figure 40). These data bits are transferred to the
Input register on the 32nd falling edge of SCLK. Commands can
be executed on individually selected DAC channels or on all DACs.
Table 7. Command Definitions
Command
C3
C2
C1
C0
Description
0
Write to Input Register n
0
1
Transfer contents of Input Register n to
DAC Register n
0
1
0
Write to Input Register n and update all
DAC Registers
0
1
Write to Input Register n and update
DAC Register n
0
1
0
Power down/power up DAC
0
1
0
1
Load clear code register
0
1
0
Load LDAC register
0
1
Reset (power-on reset)
1
0
Reserved
1
0
1
Reserved
1
Reserved
Table 8. DAC Input Register Address Bits
Address (n)
Selected DAC Channel
A3
A2
A1
A0
0
DAC A
0
1
DAC B
0
1
0
DAC C
0
1
DAC D
1
All DACs
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
XX
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
0
684
5-
0
07
Figure 40. Input Shift Register Content
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