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參數(shù)資料
| 型號(hào)： | AD5116BCPZ10-500R7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 64POS 10K 8LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 2 線按鈕 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-UFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-UD（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD5116BCPZ10-500R7DKR |
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Data Sheet
AD5116
Rev. B | Page 13 of 16
THEORY OF OPERATION
The AD5116 digital programmable resistor is designed to
operate as a true variable resistor for analog signals within
the terminal voltage range of GND < VTERM < VDD. The resistor
wiper position is determined by the RDAC register contents.
The RDAC register is a standard logic register; there is no
restriction on the number of changes allowed.
The RDAC register can be programmed with any position
setting using the push button interface. Once a desirable wiper
position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-up. The storing of EEPROM
data takes approximately 20 ms; during this time, the device
is locked and does not accept any new operation, thus
preventing any changes from taking place.
The AD5116 is designed to support external push buttons
(tactile switches) directly, as shown in Figure 1.
RDAC REGISTER
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register
is 0x20, the wiper is connected to midscale of the variable
resistor. The RDAC register is controlled using the PD and PU
push buttons. The step-up and step-down operations require
the activation of the PU (push-up) and PD (push-down) pins.
These pins have 100 kΩ internal pull-up resistors that PU and
PD activate at logic high. The following paragraphs explain how
to increment the RDAC register, but all the descriptions are
valid to decrement the RDAC register, swapping PU by PD.
Manual Increment
The AD5116 features an adaptive debouncer that monitors the
duration of the logic high level of PU signal between bounces. If
the PU logic high level signal duration is shorter than 8 ms, the
debouncer ignores it as an invalid incrementing command.
Whenever the logic high level of PU signal lasts longer than
8 ms, the debouncer assumes that the last bounce is met and,
therefore, increments the RDAC register by one step. The wiper
is incremented by one tap position, as shown in Figure 2.
Auto Scan Increment
If the PU button is held for longer than 1 second, continuously
holding it activates auto scan mode, and the AD5116 increments
the RDAC register by one step every 140 ms until PU is
released. Typical timing is shown in Figure 3.
Low Wiper Resistance Feature
The AD5116 includes extra steps to achieve a minimum wiper
resistance. Between Terminal W and Terminal B, this extra step
is called bottom scale and the wiper resistance decreases from
70 to 45 . Between Terminal A and Terminal W, this extra
step is called top scale and connects the A and W terminals,
reducing the 1 LSB resistor typical at full-scale code. These new
extra steps are loaded automatically in the RDAC register after
zero-scale or full-scale position has been reached. The extra
steps are not equal to 1 LSB, and are not included in the INL,
DNL, R-INL, and R-DNL specifications.
Whenever the minimum RWB (= RBS) is reached, the resistance
stops decrementing. Any continuous holding of the PD to logic
high simply elevates the supply current. When RAW reaches the
minimum resistance (= RTS), continuous holding of PU only
elevates the supply current.
EEPROM
The AD5116 contains an EEPROM memory that allows
wiper position storage. Once a desirable wiper position is
found, this value can be saved into the EEPROM. Thereafter,
the wiper position will always be set at that position for any
future on-off-on power supply sequence.
AUTOMATIC SAVE ENABLE
At power-up, the AD5116 checks the level in the ASE pin. If the
pin is pulled low, as shown in Figure 38, the automatic store is
enabled. If the pin is pulled high, as shown in Figure 39,
automatic store is disabled and the RDAC register should be
stored manually. During the storage cycle, the device is locked
and does not accept any new operation preventing any changes
from taking place.
09657-
036
AD5116
100k
ASE
GND
Figure 38. Automatic Store Enables
Auto Save
If there is no activity on inputs during 1 second, the AD5116
stores the RDAC register data into EEPROM, as shown in
Manual Store
The storage is controlled by the ASE pin, which is connected to
an adaptive debouncer. If the ASE pin is pulled low longer than
8 ms, the AD5116 saves the RDAC register data into EEPROM,
as shown in Figure 5.
09657-
037
AD5116
100k
ASE
VDD
Figure 39. Automatic Store Disables with Manual Storage
Push Button
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