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參數(shù)資料
| 型號(hào)： | AD5116BCPZ5-500R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 64POS 5K 8LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接片： | 64 |
| 電阻（歐姆）： | 5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | 2 線按鈕 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-UFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-UD（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD5116BCPZ5-500R7DKR |
AD5116
Data Sheet
Rev. B | Page 14 of 16
END SCALE RESISTANCE INDICATOR
When the auto save mode is enabled, the ASE pin also indicates
when the RDAC register reaches the maximum or minimum
scale. The AD5116 pulls the ASE pin high and holds it as long
as PD or PU is active, and the part is placed in the end scale
configuration is shown in Figure 40.
When the part is placed at the end of the resistance scale (RTS or
RBS), the ASE pin is pulled high during the debounce time, until
the RDAC register is incremented (RBS) or decremented (RTS) by
activating PU or PD.
09657-
038
AD5116
100k
ASE
GND
Figure 40. Typical End Scale Indicator Circuit
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5116 employs a two-stage
segmentation approach as shown in Figure 41. The AD5116
wiper switch is designed with the transmission gate CMOS
topology and with the gate voltage derived from VDD.
09657-
039
RW
SW
W
RW
6-BIT
ADDRESS
DECODER
A
TS
BS
RL
B
RL
Figure 41. Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5116 includes a new feature to reduce the
resistance between terminals. These extra steps are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 70 to 45 . At top scale, the
resistance between Terminal A and Terminal W is decreased
by 1 LSB and the total resistance is reduced to 70 . The extra
steps are not equal to 1 LSB and are not included in the INL,
DNL, R-INL, and R-DNL specifications.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5116 operates in rheostat mode when only two terminals
are used as a variable resistor. The unused terminal can be
floating or tied to the W terminal as shown in Figure 42.
09657-
040
W
A
B
W
A
B
W
A
B
Figure 42. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 5 kΩ, 10 kΩ, and 80 kΩ and has 64 tap points
accessed by the wiper terminal. The 6-bit data in the RDAC
latch is decoded to select one of the 64 possible wiper settings.
The general equation for determining the digitally programmed
output resistance between the W terminal and B terminal is:
BS
WB
R
R =
Bottom scale
(1)
W
AB
WB
R
D
R
+
×
=
64
)
(
From 0 to 64
(2)
where:
D is the decimal equivalent of the binary code in the 6-bit
RDAC register.
RAB is the end-to-end resistance.
RBS is the wiper resistance at bottom scale.
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA.
RWAstarts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equation for
this operation is:
W
AB
AW
R
+
=
Bottom scale
(3)
W
AB
AW
R
D
R
+
×
=
64
)
(
From 0 to 63
(4)
TS
AW
R
=
Top scale
(5)
where:
D is the decimal equivalent of the binary code in the 6-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
RTS is the wiper resistance at top scale.
Regardless of which setting the part is operating in, take care
to limit the current between the A terminal to B terminal, W
terminal to A terminal, and W terminal to B terminal, to the
maximum continuous current or pulsed current specified in
Table 4. Otherwise, degradation or possible destruction of
the internal switch contact can occur.
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