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參數(shù)資料
| 型號(hào)： | AD5170BRMZ2.5-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 256POS 2.5K 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 2.5k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
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AD5170
Rev. G | Page 22 of 24
After all the data bits are read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the 10th clock
pulse to establish a stop condition (see Figure 45).
In read mode, the master issues a no acknowledge for the 9th
clock pulse (that is, the SDA line remains high). The master brings
the SDA line low before the 10th clock pulse and then brings the
SDA line high to establish a stop condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in write mode, the RDAC
output updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a new
slave address, instruction, and data byte. Similarly, a repeated
read function of the RDAC is also allowed.
Multiple Devices on One Bus
Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different, which allows each device on the bus to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully
I2C-compatible interface.
SDA
AD1
AD0
MASTER
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
5V
RP RP
5V
AD1
AD0
SCL
AD5170
041
04-
047
Figure 47. Multiple AD5170s on One I2C Bus
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic con-
troller and are below the minimum VIH level (0.7 V × VDD), level
shift the signals for read/write communications between the
AD5170 and the controller. Figure 48 shows one of the implemen-
tations. For example, when SDA1 is at 2.5 V, M1 turns off and
SDA2 becomes 5 V. When the SDA1 is at 0 V, M1 turns on and
the SDA2 approaches 0 V. As a result, proper level shifting is
established. M1 and M2 should be low threshold, N-channel
power MOSFETs, such as the FDV301N.
0
410
4-
052
2.5V
CONTROLLER
2.7V TO 5.5V
AD5170
Rp
VDD1 = 2.5V
VDD2 = 5V
G
S
D
M1
S
D
M2
SDA1
SCL1
SDA2
SCL2
Figure 48. Level Shifting for Different Voltage Operation
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