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參數(shù)資料
| 型號： | AD5172BRM10 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/28頁 |
| 文件大小： | 0K |
| 描述： | IC POT DUAL 10K 256POS 10-MSOP |
| 標準包裝： | 50 |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
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AD5172/AD5173
Data Sheet
Rev. I | Page 6 of 28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Power Supply Range
VDD_RANGE
2.7
5.5
V
OTP Supply Voltage9, 10
VDD_OTP
TA = 25°C
5.6
5.7
5.8
V
Supply Current
IDD
VIH = 5 V or VIL = 0 V
3.5
6
A
OTP Supply Current9, 11, 12
IDD_OTP
VDD_OTP = 5.0 V, TA = 25°C
100
mA
Power Dissipation13
PDISS
VIH = 5 V or VIL = 0 V,
VDD = 5 V
33
W
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%,
code = midscale
±0.02
±0.08
%/%
DYNAMIC CHARACTERISTICS14
Bandwidth, 3 dB
BW
RAB = 10 k, code = 0x80
600
kHz
RAB = 50 k, code = 0x80
100
kHz
RAB = 100 k, code = 0x80
40
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 k
0.1
%
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB
error band
2
s
Resistor Noise Voltage Density
eN_WB
RWB = 5 k, RS = 0
9
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use VDD = 5 V.
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