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參數(shù)資料
| 型號(hào)： | AD5173BRM10-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers |
| 中文描述： | DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10 |
| 封裝： | 3 X 4.90 MM, MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 948K |
| 代理商： | AD5173BRM10-RL7 |
AD5172/AD5173
ESD PROTECTION
All digital inputs—SDA, SCL, AD0, and AD1— are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 39 and Figure 40.
Rev. A | Page 14 of 24
LOGIC
340
GND
0
Figure 39. ESD Protection of Digital Pins
A,B,W
GND
0
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5172/AD5173 V
DD
to GND power supply defines the
boundary conditions for proper 3-terminal digital potentiom-
eter operation. Supply signals present on terminals A, B, and W
that exceed V
DD
or GND are clamped by the internal forward-
biased diodes (see Figure 41).
GND
A
W
B
V
DD
0
Figure 41. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 41), it is important to
power V
DD
/GND before applying any voltage to terminals A, B,
and W. Otherwise, the diode will be forward biased such that
V
DD
is powered unintentionally and may affect the rest of the
user’s circuit. The ideal power-up sequence is GND, V
DD
, the
digital inputs, and then V
A
/V
B
/V
W
. The relative order of
powering V
A
, V
B
, V
W
, and the digital inputs is not important as
long as they are powered after V
DD
/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies are applied to
the same V
DD
terminal of the AD5172/AD5173. The AD5172/
AD5173 employ fuse link technology that requires 6 V to blow
the internal fuses to achieve a given setting. The user is allowed
only one attempt at blowing the fuses. Once programming is
completed, power supply voltage must be reduced to the normal
2.7 V to 5.5 V operating range. Such dual voltage requirements
require isolation between the supplies. The fuse programming
supply (either an on-board regulator or rack-mount power sup-
ply) must be rated at 6 V and must be able to provide a 100 mA
transient current for 400 ms for successful one-time program-
ming. Once programming is complete, the 6 V supply must be
removed to allow normal operation at 2.7 V to 5.5 V at regular
microamp current levels. Figure 42 shows the simplest imple-
mentation using a jumper. This approach saves one voltage
supply, but draws additional current and requires manual
configuration.
V
DD
6V
R1
50k
R2
C1
1
μ
F
C2
1nF
250k
5V
CONNECT J1 HERE
FOR OTP
CONNECT J1 HERE
AFTER OTP
AD5172/
AD5173
0
Figure 42. Power Supply Requirement
An alternate approach in 3.5 V to 5.5 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 43.
V
DD
3.5V–5.5V
6V
D1
C1
1
μ
F
C2
1nF
APPLY FOR OTP ONLY
AD5172/
AD5173
0
Figure 43. Isolate 6 V OTP Supply from 3.5 V to 5.5 V Normal Operating
Supply. The 6 V supply must be removed once OTP is completed.
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