I2
參數(shù)資料
型號: AD5173BRM50-RL7
廠商: Analog Devices Inc
文件頁數(shù): 8/28頁
文件大小: 0K
描述: IC DGTL POT DUAL 50K OTP 10-MSOP
標(biāo)準(zhǔn)包裝: 1,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
AD5172/AD5173
Data Sheet
Rev. I | Page 16 of 28
THEORY OF OPERATION
SDA
SCL
A
W
B
FUSES
EN
DAC
REG
I2C INTERFACE
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
MUX
DECODER
FUSE
REG
0
410
3-
0
26
Figure 39. Detailed Functional Block Diagram
The AD5172/AD5173 are 256-position, digitally controlled
variable resistors (VRs) that employ fuse link technology to
achieve memory retention of the resistance setting.
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function is activated, the device
powers up at the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5172/AD5173 presets to midscale
during initial power-on. After the wiper is set to the desired
position, the resistance can be permanently set by programming
the T bit high, with the proper coding (see Table 8 and Table 9),
and one-time VDD_OTP. The fuse link technology of the AD517x
family of digital potentiometers requires VDD_OTP to be between
5.6 V and 5.8 V to blow the fuses to achieve a given nonvolatile
setting. However, during operation, VDD can be 2.7 V to 5.5 V. As a
result, an external supply is required for one-time programming.
The user is allowed only one attempt to blow the fuses. If the user
fails to blow the fuses during this attempt, the structure of the
fuses can change such that they may never be blown, regardless
of the energy applied during subsequent events. For details, see
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting. Figure 39
shows a detailed functional block diagram.
Table 7. Validation Status
E1
E0
Status
0
Ready for programming.
1
0
Fatal error. Some fuses are not blown. Do not retry.
Discard this unit.
1
Successful. No further programming is possible.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal and the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the
256 possible settings.
A
W
B
A
W
B
A
W
B
04
10
3-
0
27
Figure 40. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminal W and Ter-
minal B. The second connection is the first tap point, which
corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 ×
50 Ω) for Data 0x01. The third connection is the next tap point,
representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so
on. Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
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