VW
參數(shù)資料
型號(hào)： AD5173BRM50
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT DUAL 50K OTP 10-MSOP
標(biāo)準(zhǔn)包裝： 50
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
Data Sheet
AD5172/AD5173
Rev. I | Page 5 of 28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB
error band
1
s
Resistor Noise Voltage Density
eN_WB
RWB = 1.25 k, RS = 0
3.2
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS: 10 k, 50 k, AND 100 k
VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
1
±0.1
+1
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
2.5
±0.25
+2.5
LSB
Nominal Resistor Tolerance3
ΔRAB
TA = 25°C
20
+20
%
Resistance Temperature Coefficient
(ΔRAB/RAB)/ΔT
35
ppm/°C
Wiper Resistance
RWB
Code = 0x00, VDD = 5 V
160
200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE4
Differential Nonlinearity5
DNL
1
±0.1
+1
LSB
Integral Nonlinearity5
INL
1
±0.3
+1
LSB
Voltage Divider Temperature Coefficient
(ΔVW/VW)/ΔT
Code = 0x80
15
ppm/°C
Full-Scale Error
VWFSE
Code = 0xFF
2.5
1
0
LSB
Zero-Scale Error
VWZSE
Code = 0x00
0
1
2.5
LSB
RESISTOR TERMINALS
Voltage Range6
VA, VB, VW
GND
VDD
V
Capacitance A, B7
CA, CB
f = 1 MHz, measured to
GND, code = 0x80
45
pF
Capacitance W7
CW
f = 1 MHz, measured to
GND, code = 0x80
60
pF
Shutdown Supply Current8
IA_SD
VDD = 5.5 V
0.01
1
A
Common-Mode Leakage
ICM
VA = VB = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High9
VIH
VDD = 5 V
0.7 VDD
VDD + 0.5
V
Input Logic Low9
VIL
VDD = 5 V
0.5
+0.3 VDD
V
AD0 and AD1
Input Logic High
VIH
VDD = 3 V
2.1
V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
A
Input Capacitance7
CIL
5
pF
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