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參數資料
| 型號： | AD5173BRMZ100 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL DUAL 100K OTP 10MSOP |
| 標準包裝： | 50 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數： | 2 |
| 溫度系數： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
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Data Sheet
AD5172/AD5173
Rev. I | Page 17 of 28
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
RS
A
W
B
0
41
03
-0
28
Figure 41. AD5172/AD5173 Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between W and B is
W
AB
WB
R
D
R
2
128
)
(
(1)
where:
D
is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB
is the end-to-end resistance.
RW
is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB is 10 kΩ and the A terminal is open circuited,
the output resistance, RWB, is set according to the RDAC latch
codes, as listed in Table 8.
Table 8. Codes and Corresponding RWB Resistance
D (Dec)
RWB (Ω)
Output State
255
9961
Full scale (RAB – 1 LSB + RW)
128
5060
Midscale
1
139
1 LSB
0
100
Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible destruc-
tion of the internal switch contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digi-
tally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
AB
WA
R
D
R
2
128
–
256
)
(
(2)
When RAB is 10 kΩ and the B terminal is open circuited, the
output resistance, RWA, is set according to the RDAC latch
codes, as listed in Table 9.
Table 9. Codes and Corresponding RWA Resistance
D (Dec)
RWA (Ω)
Output State
255
139
Full scale
128
5060
Midscale
1
9961
1 LSB
0
10,060
Zero scale
Typical device-to-device matching is process-lot dependent
and can vary up to ±30%. Because the resistance element is
processed using thin-film technology, the change in RAB with
temperature has a very low temperature coefficient of 35 ppm/°C.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper to B and at wiper to A, proportional to the input voltage
at A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
VI
W
B
VO
041
03
-02
9
Figure 42. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the vol-
tage applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
V
256
)
(
(3)
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
(4)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RWA and RWB, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.
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