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參數(shù)資料
| 型號： | AD5175BCPZ-10-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RHEOSTAT 5V 50-TP 1024 10MSOP |
| 標準包裝： | 1 |
| 接片： | 1024 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 標準包裝 |
| 其它名稱： | AD5175BCPZ-10-RL7DKR |
AD5175
Rev. A | Page 19 of 20
Calculate the Actual End-to-End Resistance
TERMINAL VOLTAGE OPERATING RANGE
The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance
can, therefore, be calculated (which is valuable for calibration,
tolerance matching, and precision applications).
The positive VDD and negative VSS power supplies of the AD5175
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed VDD or VSS are clamped by the internal
forward-biased diodes (see Figure 30).
The resistance tolerance in percentage is stored in fixed-point
format, using a 16-bit sign magnitude binary. The sign bit(0 =
negative and 1 = positive) and the integer part is located in
Address 0x39, as shown in Table 11. Address 0x3A contains
the fractional part, as shown in Table 12.
VSS
VDD
A
W
0
87
19
-10
9
That is, if the data readback from Address 0x39 is 0000001010
and data from Address 0x3A is 0010110000, then the end-to-end
resistance can be calculated as follows.
For Memory Location 0x39,
DB[9:8]: XX = don’t care
DB[7]: 0 = negative
Figure 30. Maximum Terminal Voltages Set by VDD and VSS
DB[6:0]: 0001010 = 10
The ground pin of the AD5175 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join
the AD5175 ground terminal remotely to the common ground.
The digital input control signals to the AD5175 must be refe-
renced to the device ground pin (GND) and satisfy the logic
level defined in the Specifications section. An internal level
shift circuit ensures that the common-mode voltage range of
the three terminals extends from VSS to VDD, regardless of the
digital input level.
For Memory Location 0x3A,
DB[9:8]: XX = don’t care
DB[7:0]: 10110000 = 176 × 28 = 0.6875
Therefore, tolerance = 10.6875% and RWA (1023)= 8.931 kΩ.
EXT_CAP CAPACITOR
A 1 μF capacitor to VSS must be connected to the EXT_CAP pin
(see Figure 29) on power-up and throughout the operation of
the AD5175.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A and Terminal W (see Figure 30), it is important to
power VDD/VSS first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD/VSS are powered unintentionally. The ideal power-up
sequence is VSS, GND, VDD, digital inputs, VA, and VW. The
order of powering VA, VW, and digital inputs is not important
as long as they are powered after VDD/VSS.
AD5175
50-TP
MEMORY
BLOCK
EXT_CAP
C1
1F
VSS
0
87
19
-009
As soon as VDD is powered, the power-on preset activates,
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.
Figure 29. EXT_CAP Hardware Setup
Table 12. End-to-End Resistance Tolerance Bytes
Data Byte1
Memory Map Address
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0x39
X
Sign
26
25
24
23
22
21
20
0x3A
X
21
22
23
24
25
26
27
28
1 X is don’t care.
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