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| 型號： | AD5201BRMZ10 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 10K 33POS 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 接片： | 33 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 500 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 3 線串行（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.3 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
AD5200/AD5201
–13–
AD5200 Wiper-to-A Resistance
DRWA
(DEC)
( )
Output State
255
50
Full-Scale (RW)
128
5030
Midscale
1
10011
1 LSB
0
10050
Zero-Scale (RAB + RW)
AD5201 Wiper-to-A Resistance
DRWA
(DEC)
( )
Output State
32
50
Full-Scale (RW)
16
5050
Midscale
1
9738
1 LSB
0
10050
Zero-Scale (RAB + RW)
The tolerance of the nominal resistance can be
±30% due to
process lot dependance. If users apply the RDAC in rheostat
(variable resistance) mode, they should be aware of such specifi-
cation of tolerance. The change in RAB with temperature has a
500 ppm/
°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input volt-
age at A to B.
Unlike the polarity of VDD – VSS, which must be positive, volt-
age across A–B, W–A, and W–B can be at either polarity.
If ignoring the effects of the wiper resistance for an approxima-
tion, connecting A terminal to 5 V and B terminal to ground
produces an output voltage at the wiper which can be any value
starting at almost zero to almost full scale with the minor devia-
tion contributed by the wiper resistance. Each LSB of voltage is
equal to the voltage applied across Terminal AB divided by the
2
N-1 and 2N position resolution of the potentiometer divider for
AD5200 and AD5201 respectively. The general equation defin-
ing the output voltage with respect to ground for any valid input
voltage applied to Terminals A and B is:
VD
D
VV
WAB
B
() =+
255
for AD5200
(5)
VD
D
VV
WAB
B
() =+
32
for AD5201
(6)
where D in AD5200 is between 0 to 255 and D in AD5201 is
between 0 to 32.
For more accurate calculation, including the effects of wiper
resistance, VW can be found as:
VD
RD
R
V
RD
R
V
W
WB
AB
A
WA
AB
B
() = () + ()
(7)
where RWB(D) and RWA(D) can be obtained from Equations
1 to 4.
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors and not
the absolute values; therefore, the drift reduces to 15 ppm/
°C.
DIGITAL INTERFACING
The AD5200/AD5201 contain a standard three-wire serial input
control interface. The three inputs are clock (CLK),
CS, and
serial data input (SDI). The positive-edge-sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means.
Figure 3 shows more detail of the internal digital circuitry. When
CS is low, the clock loads data into the serial register on each
positive clock edge (see Table III).
SER
REG
PWR-ON
PRESET
VSS
A
W
B
SHDN
RDAC
REG
Dx
8/6
VDD
CS
CLK
SDI
GND
AD5200/AD5201
Figure 3. Block Diagram
Table III. Input Logic Control Truth Table
CLK
CS
SHDN
Register Activity
L
H
No SR effect.
P
L
H
Shift one bit in from the SDI pin.
X
P
H
Load SR data into RDAC latch.
X
H
No operation.
X
H
L
Open circuit on A terminal and short
circuit between W to B terminals.
NOTE
P = positive edge, X = don’t care, SR = shift register.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 4. Applies to
digital input pins
CS, SDI, SHDN, CLK.
340
LOGIC
VSS
Figure 4. ESD Protection of Digital Pins
A,B,W
VSS
Figure 5. ESD Protection of Resistor Terminals
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