參數(shù)資料
型號(hào)： AD5201BRMZ50
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 8/15頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT 50K 33POS 10-MSOP
標(biāo)準(zhǔn)包裝： 50
接片： 33
電阻（歐姆）： 50k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 500 ppm/°C
存儲(chǔ)器類(lèi)型： 易失
接口： 3 線(xiàn)串行（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V，±2.3 V ~ 2.7 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
–2–
AD5200/AD5201–SPECIFICATIONS
AD5200 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
RWB, VA = No Connect
–1
± 0.25 +1
LSB
Resistor Integral Nonlinearity
2
R-INL
RWB, VA = No Connect
–2
± 0.5 +2
LSB
Nominal Resistor Tolerance
3
R
AB
TA = 25
°C
–30
+30
%
Resistance Temperature Coefficient
RAB/
TV
AB = V DD, Wiper = No Connect
500
ppm/
°C
Wiper Resistance
RW
VDD = 5 V
50
100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
Resolution
N
8
Bits
Differential Nonlinearity
4
DNL
–1
± 1/4 +1
LSB
Integral Nonlinearity
4
INL
–2
± 1/2 +2
LSB
Voltage Divider Temperature Coefficient
V
W/
T
Code = 80 H
5
ppm/
°C
Full-Scale Error
VWFSE
Code = FF H
–1.5
–0.5
0
LSB
Zero-Scale Error
VWZSE
Code = 00 H
0
+0.5
+1.5
LSB
RESISTOR TERMINALS
Voltage Range
5
VA, B, W
VSS
VDD
V
Capacitance
6 A, B
CA, B
f = 1 MHz, Measured to GND, Code = 80 H
45
pF
Capacitance
6 WC
W
f = 1 MHz, Measured to GND, Code = 80 H
60
pF
Shutdown Supply Current
7
IDD_SD
VDD = 5.5 V
0.01
5
A
Common-Mode Leakage
ICM
VA = VB = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VIH
2.4
V
Input Logic Low
VIL
0.8
V
Input Logic High
VIH
VDD = 3 V, VSS = 0 V
2.1
V
Input Logic Low
VIL
VDD = 3 V, VSS = 0 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
A
Input Capacitance
6
CIL
5pF
POWER SUPPLIES
Logic Supply
VLOGIC
2.7
5.5
V
Power Single-Supply Range
VDD RANGE
VSS = 0 V
–0.3
5.5
V
Power Dual-Supply Range
VDD/SS RANGE
± 2.3
± 2.7
V
Positive Supply Current
IDD
VIH = +5 V or VIL = 0 V
15
40
A
Negative Supply Current
ISS
VSS = –5 V
15
40
A
Power Dissipation
8
PDISS
VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = 0 V
0.2
mW
Power Supply Sensitivity
PSS
V
DD = +5 V
± 10%, Code = Midscale
–0.01 0.001 +0.01
%/%
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth –3 dB
BW_10 k
RAB = 10 k
, Code = 80
H
600
kHz
BW_50 k
RAB = 50 k
, Code = 80
H
100
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 k
0.003
%
VW Settling Time (10 k
/50 k)t
S
VA = 5 V, VB = 0 V,
± 1 LSB Error Band
2/9
s
Resistor Noise Voltage Density
eN_WB
RWB = 5 k
, RS = 0
9
nV
√Hz
NOTES
1Typicals represent average readings at 25
°C and VDD = 5 V, VSS = 0 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V,
VSS = –2.7 V.
3V
AB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL
specification limits of
± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Measured at the A terminal. A terminal is open-circuited in shutdown mode.
8P
DISS is calculated from (IDD
× VDD). CMOS logic level inputs result in minimum power dissipation.
9All dynamic characteristics use V
DD = 5 V, VSS = 0 V.
Specifications subject to change without notice.
(VDD = 5 V
10%, or 3 V
10%, VSS = 0 V, VA = +VDD, VB = 0 V,
–40 C < TA < +85 C unless otherwise noted.)
REV. D
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