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參數(shù)資料
| 型號(hào)： | AD5231BRUZ100-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 100K 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 1024 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 600 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 非易失 |
| 接口： | 4 線(xiàn) SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5231
Data Sheet
Rev. D | Page 16 of 28
TERMINAL VOLTAGE OPERATION RANGE
The AD5231’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on the A, B,
and W terminals that exceed VDD or VSS are clamped by the
internal forward-biased diodes (see Figure 40).
The ground pin of the AD5231 device is primarily used as a
digital ground reference, which needs to be tied to the common
ground of the PCB. The digital input control signals to the
AD5231 must be referenced to the device ground pin (GND)
and satisfy the logic level defined in the Specifications section.
An internal level-shift circuit ensures that the common-mode
voltage range of the three terminals extends from VSS to VDD,
regardless of the digital input level.
VSS
VDD
A
W
B
02739-
039
Figure 40. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at the
A, B, and W terminals (Figure 40), it is important to power
VDD/VSS first before applying any voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forward-
biased such that VDD/VSS are powered unintentionally and
might affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, VSS, digital inputs, and VA/VB/VW. The
order of powering VA, VB, VW, and digital inputs is not
important as long as they are powered after VDD/VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on preset
remains effective, which restores the EEMEM value to the
RDAC register.
LATCHED DIGITAL OUTPUTS
A pair of digital outputs, O1 and O2, is available on the
AD5231. These outputs provide a nonvolatile Logic 0 or Logic 1
setting. O1 and O2 are standard CMOS logic outputs, shown in
Figure 41. These outputs are ideal to replace the functions often
provided by DIP switches. In addition, they can be used to drive
other standard CMOS logic-controlled parts that need an
occasional setting change. Pin O1 and Pin O2 default to Logic 1,
and they can drive up to 50 mA of load at 5 V/25°C.
VDD
GND
OUTPUTS
O1 AND O2
PINS
02739-
040
Figure 41. Logic Outputs O1 and O2
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