VDD
參數(shù)資料
型號(hào): AD5245BRJZ50-RL7
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC DGTL POT 256POS 50K SOT23-8
標(biāo)準(zhǔn)包裝: 1
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 45 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 787 (CN2011-ZH PDF)
其它名稱: AD5245BRJZ50-RL7DKR
AD5245
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS
5 K, 10 K, 50 K, 100 K VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS2, ,3 4 (Specifications Apply to All Parts)
SCL Clock Frequency
fSCL
400
kHz
tBUF Bus Free Time Between STOP and START
t1
1.3
s
tHD;STA Hold Time (Repeated START)
t2
After this period, the first clock
pulse is generated.
0.6
s
tLOW Low Period of SCL Clock
t3
1.3
s
tHIGH High Period of SCL Clock
t4
0.6
s
tSU;STA Setup Time for Repeated START Condition
t5
0.6
s
tHD;DAT Data Hold Time
t6
0.9
s
tSU;DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300
ns
tR Rise Time of Both SDA and SCL Signals
t9
300
ns
tSU;STO Setup Time for STOP Condition
t10
0.6
s
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See timing diagram (
) for locations of measured values.
4 Standard I2C mode operation guaranteed by design.
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