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| 型號： | AD5252BRU100-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DCP DUAL 100K 256POS 14TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 650 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5251/AD5252
Data Sheet
Rev. D | Page 22 of 28
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that
requires a pull-up resistor for proper communication. On the
other hand, SCL and WP are digital inputs for which pull-up
resistors are recommended to minimize the MOSFET cross-
conduction current when the driving signals are lower than
VDD. SCL and WP have ESD protection diodes, as shown in
Figure 35 and Figure 36.
WP can be permanently tied to VDD without a pull-up resistor if
the write-protect feature is not used. If WP is left floating, an
internal current source pulls it low to enable write protection. In
applications in which the device is programmed infrequently,
this allows the part to default to write-protection mode after
any one-time factory programming or field calibration without
using an on-board pull-down resistor. Because there are
protection diodes on all inputs, the signal levels must not be
greater than VDD to prevent forward biasing of the diodes.
03823-0-035
GND
SCL
VDD
Figure 35. SCL Digital Input
03823-0-036
GND
INPUTS
WP
VDD
Figure 36. Equivalent WP Digital Input
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins,
AD1 and AD0, that allow up to four AD5251/AD5252 devices
to be operated on one I2C bus. To achieve this result, the states of
AD1 and AD0 on each device must first be defined. An example
device is issued a different slave address—01011(AD1)(AD0)—
to complete the addressing.
Table 12. Multiple Devices Addressing
AD1
AD0
Device Addressed
0
U1
0
1
U2
1
0
U3
1
U4
03823-0-037
5V
RP
5V
U1
AD0
AD1
SDA SCL
MASTER
U2
AD0
AD1
SDA SCL
U3
AD0
AD1
SDA SCL
U4
AD0
AD1
SDA
SCL
Figure 37. Multiple AD5251/AD5252 Devices on a Single Bus
TERMINAL VOLTAGE OPERATION RANGE
The AD5251/AD5252 are designed with internal ESD diodes
for protection; these diodes also set the boundaries for the
terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. Similarly, negative signals
on Terminal A, Terminal B, or Terminal W that are more
users should not operate VAB, VWA, and VWB to be higher than
the voltage across VDD to VSS, but VAB, VWA, and VWB have no
polarity constraint.
VSS
V
A
W
B
03823-0-018
Figure 38. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 38), it is
important to power on VDD/VSS before applying any voltage to
these terminals. Otherwise, the diodes are forward biased such
that VDD/VSS are powered unintentionally and may affect the
user’s circuit. Similarly, VDD/VSS should be powered down last.
The ideal power-up sequence is in the following order: GND,
VDD, V, digital inputs, and VA/VB/VW. The order of powering
VA, VB, VW, and the digital inputs is not important, as long as
they are powered after VDD/VSS.
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