參數(shù)資料
型號(hào): AD5252BRU10
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字電位計(jì)
英文描述: 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23
中文描述: DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
封裝: MO-153AB-1, TSSOP-14
文件頁(yè)數(shù): 9/28頁(yè)
文件大?。?/td> 859K
代理商: AD5252BRU10
AD5251/AD5252
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Rev. 0 | Page 9 of 28
1
2
3
4
5
6
7
AD0
WP
W1
SDA
A1
B1
V
DD
14
13
12
11
10
9
8
B3
A3
AD1
V
SS
SCL
DGND
W3
0
AD5251/
AD5252
TOP VIEW
(Not to Scale)
Figure 2. AD5251/AD5252 in TSSOP-14
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
V
DD
Description
Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply,
where V
DD
– V
SS
≤ 5.5 V. V
DD
must be able to source 35 mA for 26 ms when storing data to
EEMEM.
I
2
C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed.
Write Protect, Active Low. V
WP
≤ V
DD
+ 0.3 V.
Wiper Terminal of RDAC1. V
SS
≤ V
W1
≤ V
DD
.
1
B Terminal of RDAC1. V
SS
≤ V
B1
≤ V
DD
.
1
A Terminal of RDAC1. V
SS
≤ V
A1
≤ V
DD
.
1
Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded
first. Open-drain MOSFET requires pull-up resistor.
Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V
DD
– V
SS
+5.5 V. If V
SS
is used, other than grounded, in dual supply, V
SS
must be able to sink 35 mA for
26 ms when storing data to EEMEM.
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. V
SCL
(V
DD
+ 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power.
Digital Ground. Connect to system analog ground at a single point.
I
2
C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed.
A Terminal of RDAC3. V
SS
≤ V
A3
≤ V
DD
.
1
B Terminal of RDAC3. V
SS
≤ V
B3
≤ V
DD
.
1
W Terminal of RDAC3. V
SS
≤ V
W3
≤ V
DD
.
1
2
3
4
5
6
7
AD0
WP
W1
B1
A1
SDA
8
V
SS
9
SCL
10
11
12
13
14
DGND
AD1
A3
B3
W3
1
For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.
I
2
C INTERFACE TIMING DIAGRAM
t
1
SCL
SDA
P
S
P
0
t
3
t
2
t
8
t
9
t
8
t
9
t
4
t
5
t
7
t
6
t
10
Figure 3. I
2
C Timing Diagram
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