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參數(shù)資料
| 型號： | AD5254BRU1-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Dual, 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers |
| 中文描述： | QUAD 1K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 834K |
| 代理商： | AD5254BRU1-RL7 |
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AD5253/AD5254
Rev. 0 | Page 22 of 28
0
+5V
R1
AD1
AD0
N1
4
2
×
4
+5V
R2
X
AD1
AD0
N2
X
+5
P2
Y
P2
Y
P3
X
R3
X
R3
Y
N3
Y
AD1
AD0
AD1
AD0
×
4
×
4
×
4
+5V
P4
R4
+5V
2
×
4
DECODER
4
2
×
4
DECODER
4
2
×
4
DECODER
4
2
×
4
DECODER
Figure 38. Four Devices with AD1 and AD0 of 00
TERMINAL VOLTAGE OPERATION RANGE
The AD5253/AD5254 are designed with internal ESD diodes
for protection; these diodes also set the boundary of the
terminal operating voltages. Positive signals present on terminal
A, B, or W that exceed V
DD
are clamped by the forward biased
diode. Similarly, negative signals on terminal A, B, or W that are
more negative than V
SS
are also clamped (see Figure 39). In
practice, users should not operate V
AB
, V
WA
, and V
WB
to be
higher than the voltage across V
DD
-to-V
SS
, but V
AB
, V
WA
, and V
WB
have no polarity constraint.
0
V
DD
A
W
B
V
SS
Figure 39. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP AND POWER-DOWN SEQUENCES
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (Figure 39), it is important to power
V
DD
/V
SS
before applying any voltage to terminals A, B, and W.
Otherwise, the diodes are forward-biased such that V
DD
/V
SS
are
powered unintentionally and may affect the rest of the user’s
circuit. Similarly, V
DD
/V
SS
should be powered down last. The
ideal power-up sequence is in the following order: GND, V
DD
,
V
SS
, digital inputs, and V
A
/V
B
/V
W
. The order of powering V
A
, V
B
,
V
W
, and the digital inputs is not important, as long as they are
powered after V
DD
/V
SS
.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum
lead-length layout design. The leads to the input should be as
direct as possible, with a minimum conductor length. Ground
paths should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors. Low ESR (equivalent series resistance)
1 μF to 10 μF tantalum or electrolytic capacitors should be
applied at the supplies to minimize any transient disturbance
and filter low frequency ripple. Figure 40 illustrates the basic
supply-bypassing configuration for the AD5253/AD5254.
0
V
DD
V
DD
V
SS
V
SS
GND
C3
AD5253/AD5254
C4
C1
C2
10
μ
F
10
μ
F
0.1
μ
F
0.1
μ
F
Figure 40. Power Supply Bypassing
The ground pin of the AD5253/AD5254 is used primarily as a
digital ground reference. To minimize the digital ground
bounce, the AD5253/AD5254 ground terminal should be joined
remotely to the common ground (see Figure 40).
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