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參數(shù)資料
| 型號(hào)： | AD5255BRU250 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 3-Channel Digital Potentiometer with Nonvolatile Memory |
| 中文描述： | TRIPLE 250K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 512 POSITIONS, PDSO24 |
| 封裝： | MO-153AD, TSSOP-24 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 626K |
| 代理商： | AD5255BRU250 |
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AD5255
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 7 of 20
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
19
18
17
16
15
14
13
12
11
NC = NO CONNECT
A1_RDAC
A0_RDAC
RS
SDA
SCL
WP
A0_EE
TEST0 (NC)
TEST1 (NC)
TEST2 (NC)
A0
C
DD
, AV
DD
TEST3 (NC)
DGND
V
SS
, AV
SS
B2
W2
A2
W0
B0
A1
W1
B1
A1_EE
AD5255
TOP VIEW
(Not to Scale)
0
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
1
A1_EE
2
A1_RDAC
3
A0_RDAC
4
RS
Description
I
2
C Device Address 1 for EEMEM.
I
2
C Device Address 1 for RDAC.
I
2
C Device Address 0 for RDAC.
Resets the scratchpad register with current contents of the EEMEM register. Factory defaults to midscale before
any programming.
Write Protect. When active low, WP prevents any changes to the present register contents, except that RESET
and Commands 1 and 8 still refresh the RDAC register from EEMEM.
Serial Input Register Clock. Shifts in one bit at a time on the positive clock edges.
Serial Data Input. Shifts in one bit at a time on the positive clock edges. The MSB is loaded first.
Ground. Logic ground reference.
Negative Supply. Connect to 0 V for single-supply applications.
A terminal of RDAC2.
Wiper terminal of RDAC2.
B terminal of RDAC2.
A terminal of RDAC1.
Wiper terminal of RDAC1.
B terminal of RDAC1.
B terminal of RDAC0.
Wiper terminal of RDAC0.
A terminal of RDAC0.
Positive Power Supply.
Test Pin 3. Do not connect.
Test Pin 2. Do not connect.
Test Pin 1. Do not connect.
Test Pin 0. Do not connect.
I
2
C Device Address 0 for EEMEM.
5
WP
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCL
SDA
DGND
V
SS
A2
W2
B2
A1
W1
B1
B0
W0
A0
V
DD
TEST3
TEST2
TEST1
TEST0
A0_EE
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