參數(shù)資料
型號(hào): AD5258BRMZ1
廠商: Analog Devices Inc
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: IC POT DGTL I2C1K 64P 10MSOP
標(biāo)準(zhǔn)包裝: 50
接片: 64
電阻(歐姆): 1k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 200 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
產(chǎn)品目錄頁面: 787 (CN2011-ZH PDF)
配用: AD5258EVAL-ND - BOARD EVAL FOR AD5258 DGTL POT
AD5258
Data Sheet
Rev. D | Page 14 of 24
THEORY OF OPERATION
The AD5258 is a 64-position digitally controlled variable
resistor (VR) device. The wipers default value prior to pro-
gramming the EEPROM is midscale.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 1 k, 10 k, 50 k, and 100 k.
The nominal resistance of the VR has 64 contact points accessed
by the wiper terminal. The 6-bit data in the RDAC latch is
decoded to select one of 64 possible settings.
A
W
B
A
W
B
A
W
B
05029-
037
Figure 36. Rheostat Mode Configuration
The general equation determining the digitally programmed
output resistance between Wiper W and Terminal B is
( )
W
AB
WB
R
D
R
×
+
×
=
2
64
(1)
where:
D is the decimal equivalent of the binary code loaded in the
6-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
each internal switch.
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
RS
A
W
B
05029-
038
Figure 37. AD5258 Equivalent RDAC Circuit
Note that in the zero-scale condition, there is a relatively
low value finite wiper resistance. Care should be taken to
limit the current flow between Wiper W and Terminal B in
this state to a maximum pulse current of no more than 20 mA.
Otherwise, degradation or destruction of the internal switch
contact may occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, RWA. The resistance value
setting for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value.
The general equation for this operation is
( )
W
AB
WA
R
D
R
×
+
×
=
2
64
(2)
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. For this reason, resistance tolerance is
stored in the EEPROM such that the user will know the actual
RAB within 0.1%.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W-to-Terminal B and Wiper W-to-Terminal A propor-
tional to the input voltage at Terminal A-to-Terminal B. Unlike
the polarity of VDD-to-GND, which must be positive, voltage
across Terminal A-to-Terminal B, Wiper W-to-Terminal A,
and Wiper W-to-Terminal B can be at either polarity.
A
VI
W
B
VO
05029-
039
Figure 38. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W-to-Terminal B starting
at 0 V up to 1 LSB less than 5 V. The general equation defining
the output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
( )
B
A
W
V
D
V
D
V
64
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance (VW) is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of internal resistors (RWA and RWB) and not the abso-
lute values.
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