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參數(shù)資料
| 型號： | AD5259BCPZ100-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Nonvolatile, I2C-Compatible 256-Position, Digital Potentiometer |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, DSO10 |
| 封裝： | 3 X 3 MM, 0.80 MM HEIGHT, LEAD FREE, LFCSP-10 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 1039K |
| 代理商： | AD5259BCPZ100-R7 |
AD5259
THEORY OF OPERATION
The AD5259 is a 256-position digitally-controlled variable
resistor (VR) device. EEPROM is pre-loaded at midscale from
the factory, and initial power-up is, accordingly, at midscale.
Rev. A | Page 14 of 24
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (R
AB
) of the RDAC between Terminal A
and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance of the VR has 256 contact points accessed
by the wiper terminal. The 8-bit data in the RDAC latch is
decoded to select one of 256 possible settings.
A
W
B
A
W
B
A
W
B
0
Figure 38. Rheostat Mode Configuration
The general equation determining the digitally programmed
output resistance between Wiper W and Terminal B is
W
AB
WB
R
R
D
D
R
×
+
×
=
2
256
)
(
(1)
where:
D
is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the ON resistance of
each internal switch.
D4
D3
D2
D1
D0
D7
D5
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
0
Figure 39. AD5259 Equivalent RDAC Circuit
In the zero-scale condition, there is a relatively low value finite
wiper resistance. Care should be taken to limit the current flow
between Wiper W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, R
WA
. The resistance value
setting for R
WA
starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
AB
WA
R
R
D
D
R
×
+
×
=
2
256
256
)
(
(2)
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. For this reason, resistance tolerance is
stored in the EEPROM, enabling the user to know the actual
R
AB
within 0.1%.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W to Terminal B and Wiper W to Terminal A propor-
tional to the input voltage at Terminal A to Terminal B. Unlike
the polarity of V
DD
to GND, which must be positive, voltage
across Terminal A to Terminal B, Wiper W to Terminal A, and
Wiper W to Terminal B can be at either polarity.
A
V
I
W
B
V
O
0
Figure 40. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W to Terminal B starting
at 0 V up to 1 LSB less than 5 V. The general equation defining
the output voltage at V
W
with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance, V
W
, is
B
AB
WA
R
A
AB
WB
R
W
V
D
R
V
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the Internal Resistors R
WA
and R
WB
and not
the absolute values.
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