Typ1 Max Unit Total Harmonic Distor" />
參數(shù)資料
型號(hào)： AD5280BRUZ50-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/28頁(yè)
文件大小： 0K
描述： IC DGTL POT 50K +15V 14-TSSOP
標(biāo)準(zhǔn)包裝： 1,000
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 30 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C（設(shè)備位址）
電源電壓： 4.5 V ~ 16.5 V，±4.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
其它名稱： AD5280BRUZ50REEL7
AD5280/AD5282
Rev. C | Page 4 of
28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Total Harmonic Distortion
THDW
VA = 1 V rms, RAB = 20 kΩ
0.014
%
VB = 0 V dc, f = 1 kHz
VW Settling Time
tS
VA = 5 V, VB = 5 V, ±1 LSB error band
5
μs
Crosstalk
CT
VA = VDD, VB = 0 V, measure VW1 with
adjacent RDAC making full-scale
code change
15
nV-s
Analog Crosstalk
CTA
Measure VW1 with VW2 = 5 V p-p @ f =
10 kHz
62
dB
Resistor Noise Voltage
eN_WB
RWB = 20 kΩ, f = 1 kHz
18
nV/√Hz
INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time Between
Stop and Start
t1
1.3
μs
tHD:STA Hold Time (Repeated
Start)
t2
After this period, the first clock pulse
is generated
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
μs
tSU:STA Setup Time for Start
Condition
t5
0.6
μs
tHD:DAT Data Hold Time
t6
0
0.9
μs
tSU:DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and
SCL Signals
t8
300
ns
tR Rise Time of Both SDA and
SCL Signals
t9
300
ns
tSU:STO Setup Time for STOP
Condition
t10
0.6
μs
02
92
9-
0
42
1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram (Figure 3) for location of measured values.
11 Standard I2C mode operation is guaranteed by design.
t1
t2
t3
t8
t9
t6
t4
t7
t5
t2
t10
PS
S
SCL
SDA
P
Figure 3. Detailed Timing Diagram
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