CW 85pF RDAC CIRCUIT SIMULATION MODEL The internal p" />
參數(shù)資料
型號: AD5282BRUZ50-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 17/28頁
文件大小: 0K
描述: IC POT DGTL 50K 256POS 16TSSOP
標準包裝: 1,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標準值 30 ppm/°C
存儲器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 16.5 V,±4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
AD5280/AD5282
Rev. C | Page 24 of
28
02
92
9-
0
68
CW
85pF
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the 3 dB bandwidth of the AD5280
(20 kΩ resistor) measures 310 kHz at half scale. Figure 24
provides the Bode plot characteristics of the three available
resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic
simulation model is shown in Figure 65. A macro model net list
for the 20 kΩ RDAC is provided.
CA
25pF
CA
25pF
RDAC
20k
A
B
Figure 65. RDAC Circuit Simulation Model for RDAC = 20 kΩ
MACRO MODEL NET LIST FOR RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA
A
0
25E-12
RWA
A
W
{(1-D/256)*RDAC+60}
CW
W
0
55E-12
RWB
W
B
{D/256*RDAC+60}
CB
B
0
25E-12
*
.ENDS DPOT
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