參數(shù)資料
型號(hào)： AD5304ARM
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 8BIT QUAD VOUT 10-MSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 50
設(shè)置時(shí)間： 6µs
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 4.5W
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸出數(shù)目和類(lèi)型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 167k
Data Sheet
AD5304/AD5314/AD5324
Rev. H | Page 17 of 24
AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
Figure 37 shows a serial interface between the AD5304/AD5314/
AD5324 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5304/AD5314/AD5324,
while the MOSI output drives the serial data line (DIN) of the
DAC. The SYNC signal is derived from a port line (PC7). The
setup conditions for the correct operation of this interface are as
follows: the 68HC11/68L11 is configured so that its CPOL bit is
a 0 and its CPHA bit is a 1. When data is being transmitted to the
DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11
is configured as above, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5304/ AD5314/AD5324, PC7 is left
low after the first eight bits are transferred, a second serial write
operation is performed to the DAC, and PC7 is taken high at
the end of this procedure.
AD5304/
AD5314/
AD5324*
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SCK
DIN
MOSI
SYNC
PC7
0
09
29
-03
7
Figure 37. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
AD5304/AD5314/AD5324 to 80C51/80L51 Interface
Figure 38 shows a serial interface between the AD5304/AD5314/
AD5324 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5304/AD5314/AD5324, while RxD drives the serial
data line of the part. The SYNC signal is again derived from a
bit-programmable pin on the port. In this case, port line P3.3 is
used. When data is to be transmitted to the AD5304/AD5314/
AD5324, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in a format that has the LSB first. The AD5304/
AD5314/AD5324 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine takes this into
account.
AD5304/
AD5314/
AD5324*
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
TxD
DIN
RxD
SYNC
P3.3
0
09
29
-03
8
Figure 38. AD5304/AD5314/AD5324 to 80C51/80L51 Interface
AD5304/AD5314/AD5324 to MICROWIRE Interface
Figure 39 shows an interface between the AD5304/AD5314/
AD5324 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5304/AD5314/AD5324 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
AD5304/
AD5314/
AD5324*
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SK
DIN
SO
SYNC
CS
0
09
29
-03
9
Figure 39. AD5304/AD5314/AD5324 to MICROWIRE Interface
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