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參數(shù)資料
| 型號： | AD5305ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 427K |
| 代理商： | AD5305ARM-REEL7 |
REV. F
–2–
AD5305/AD5315/AD5325–SPECIFICATIONS
C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
(V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k to GND;
A Version
2
Min
B Version
2
Min
Parameter
1
Typ
Max
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5305
Resolution
Relative Accuracy
Differential Nonlinearity
8
±
0.15
±
0.02
8
±
0.15
±
0.02
Bits
LSB
LSB
±
1
±
0.25
±
0.625
±
0.25
Guaranteed Monotonic by Design
over All Codes
AD5315
Resolution
Relative Accuracy
Differential Nonlinearity
10
±
0.5
±
0.05
10
±
0.5
±
0.05
Bits
LSB
LSB
±
4
±
0.5
±
2.5
±
0.5
Guaranteed Monotonic by Design
over All Codes
AD5325
Resolution
Relative Accuracy
Differential Nonlinearity
12
±
2
±
0.2
12
±
2
±
0.2
Bits
LSB
LSB
±
16
±
1
±
10
±
1
Guaranteed Monotonic by Design
over All Codes
Offset Error
Gain Error
Lower Deadband
±
0.4
±
0.15
20
±
3
±
1
60
±
0.4
±
0.15
20
±
3
±
1
60
% of FSR
% of FSR
mV
Lower deadband exists only if
offset error is negative.
Offset Error Drift
5
Gain Error Drift
5
Power Supply Rejection Ratio
5
DC Crosstalk
–12
–5
–60
200
–12
–5
–60
200
ppm of FSR/
°
C
ppm of FSR/
°
C
dB
μ
V
V
=
±
10%
R
L
= 2 k
to GND or V
DD
DAC REFERENCE INPUTS
5
V
REF
Input Range
V
REF
Input Impedance
0.25
37
V
DD
0.25
37
V
DD
V
k
M
dB
45
>10
–90
45
>10
–90
Normal Operation
Power-Down Mode
Frequency = 10 kHz
Reference Feedthrough
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
0.001
0.001
V
This is a measure of the minimum
and maximum drive capability
of the output amplifier.
Maximum Output Voltage
6
DC Output Impedance
Short Circuit Current
V
DD
– 0.001
0.5
25
16
2.5
V
DD
– 0.001
0.5
25
16
2.5
V
mA
mA
μ
s
V
DD
= 5 V
V
= 3 V
Coming out of Power-Down Mode.
V
= 5 V
Coming out of Power-Down Mode.
V
DD
= 3 V
Power-Up Time
5
5
μ
s
LOGIC INPUTS (A0)
5
Input Current
V
IL
, Input Low Voltage
±
1
0.8
0.6
0.5
±
1
0.8
0.6
0.5
μ
A
V
V
V
V
V
V
pF
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
V
DD
= 2.5 V
V
IH
, Input High Voltage
2.4
2.1
2.0
2.4
2.1
2.0
Pin Capacitance
3
3
LOGIC INPUTS (SCL, SDA)
5
V
IH
, Input High Voltage
V
IL
, Input Low Voltage
I
IN
, Input Leakage Current
V
HYST
, Input Hysteresis
C
Glitch Rejection
0.7 V
DD
–0.3
V
+ 0.3
0.3 V
DD
±
1
0.7 V
DD
–0.3
V
+ 0.3
0.3 V
DD
±
1
V
V
μ
A
V
pF
ns
SMBus Compatible at V
DD
< 3.6 V
SMBus Compatible at V
DD
< 3.6 V
0.05 V
DD
0.05 V
DD
8
8
50
50
Input filtering suppresses noise
spikes of less than 50 ns.
LOGIC OUTPUT (SDA)
5
V
OL
, Output Low Voltage
0.4
0.6
±
1
0.4
0.6
±
1
V
V
μ
A
pF
I
SINK
= 3 mA
I
SINK
= 6 mA
Three-State Leakage Current
Three-State Output Capacitance
8
8
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