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| 型號(hào)： | AD5305BRM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | AD5305BRM-REEL |
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REV. F
–4–
AD5305/AD5315/AD5325
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter
(A, B Version)
Unit
Conditions/Comments
f
SCL
t
1
t
2
t
3
t
4
t
5
t
63
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1C
B4
400
kHz max
μ
s min
μ
s min
μ
s min
μ
s min
ns min
μ
s max
μ
s min
μ
s min
μ
s min
μ
s min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
SU,DAT
, Data Setup Time
t
HD,DAT
, Data Hold Time
t
HD,DAT
, Data Hold Time
t
SU,STA
, Setup Time for Repeated Start
t
SU,STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time between a STOP and a START Condition
t
R
, Rise Time of SCL and SDA when Receiving
t
R
, Rise Time of SCL and SDA when Receiving (CMOS Compatible)
t
F
, Fall Time of SDA when Transmitting
t
F
, Fall Time of SDA when Receiving (CMOS Compatible)
t
F
, Fall Time of SCL and SDA when Receiving
t
F
, Fall Time of SCL and SDA when Transmitting
Capacitive Load for Each Bus Line
t
7
t
8
t
9
t
10
t
11
C
B
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Specifications subject to change without notice.
SCL
SDA
START
CONDITION
t
9
t
3
t
4
t
6
t
2
t
5
t
t
8
t
1
t
4
t
11
t
10
REPEATED
START
CONDITION
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
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