參數(shù)資料
型號: AD5305BRMZ
廠商: Analog Devices Inc
文件頁數(shù): 11/24頁
文件大?。?/td> 0K
描述: IC DAC 8BIT 2WIRE I2C 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 50
設(shè)置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 5mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5305/AD5315/AD5325
Rev. G | Page 19 of 24
When both bits are set to 0, the DAC works normally with its
normal power consumption of 600 μA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (80 nA at 3 V). Not only does the supply current drop, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has an
advantageous because the output impedance of the part is known
while the part is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. There are three different options. The output is
connected internally to GND through a 1 kΩ resistor, a 100 kΩ
resistor, or it is left open-circuited (three-state). Resistor
tolerance = ±20%. The output stage is illustrated in Figure 35.
AMPLIFIER
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
VOUT
RESISTOR
NETWORK
0
93
0-
0
35
Figure 35. Output Stage During Power-Down
The bias generator, the output amplifiers, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
DAC registers are unchanged when in power-down. The time to
exit power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
VDD = 3 V. This is the time from the rising edge of the eighth
SCL pulse to when the output voltage deviates from its power-
down voltage. See Figure 21 for a plot.
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