參數(shù)資料
型號(hào): AD5307
廠商: Analog Devices, Inc.
英文描述: 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
中文描述: 2.5 V至5.5 V,500微安,2線接口四路電壓輸出數(shù)模轉(zhuǎn)換器8-/10-/12-Bit
文件頁數(shù): 4/20頁
文件大?。?/td> 427K
代理商: AD5307
REV. F
–4–
AD5305/AD5315/AD5325
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter
(A, B Version)
Unit
Conditions/Comments
f
SCL
t
1
t
2
t
3
t
4
t
5
t
63
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1C
B4
400
kHz max
μ
s min
μ
s min
μ
s min
μ
s min
ns min
μ
s max
μ
s min
μ
s min
μ
s min
μ
s min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
SU,DAT
, Data Setup Time
t
HD,DAT
, Data Hold Time
t
HD,DAT
, Data Hold Time
t
SU,STA
, Setup Time for Repeated Start
t
SU,STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time between a STOP and a START Condition
t
R
, Rise Time of SCL and SDA when Receiving
t
R
, Rise Time of SCL and SDA when Receiving (CMOS Compatible)
t
F
, Fall Time of SDA when Transmitting
t
F
, Fall Time of SDA when Receiving (CMOS Compatible)
t
F
, Fall Time of SCL and SDA when Receiving
t
F
, Fall Time of SCL and SDA when Transmitting
Capacitive Load for Each Bus Line
t
7
t
8
t
9
t
10
t
11
C
B
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Specifications subject to change without notice.
SCL
SDA
START
CONDITION
t
9
t
3
t
4
t
6
t
2
t
5
t
t
8
t
1
t
4
t
11
t
10
REPEATED
START
CONDITION
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
相關(guān)PDF資料
PDF描述
AD5305BRM 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5315BRM 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305ARM 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305ARM-REEL7 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305BRM-REEL 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD53071-01 制造商:Analog Devices 功能描述:
AD5307ARU 制造商:Analog Devices 功能描述:DAC 4-CH Resistor-String 8-bit 16-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:8-BIT QUAD DAC I.C. - Bulk
AD5307ARU-REEL7 制造商:Analog Devices 功能描述:DAC 4-CH Resistor-String 8-bit 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 4-CH RES-STRING 8BIT 16TSSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:8-BIT QUAD DAC I.C. - Tape and Reel
AD5307ARUZ 功能描述:IC DAC 8BIT QUAD W/BUFF 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行,SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散(最大):- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC(0.154",3.90mm 寬) 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓,單極;1 電壓,雙極 采樣率(每秒):* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD5307ARUZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 400 muA, Quad Voltage Output