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參數(shù)資料
| 型號(hào)： | AD5310BRM |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT R-R W/BUFF 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.25mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 167k |
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Data Sheet
AD5310
Rev. B | Page 13 of 16
AD5310 to 68HC11/68L11 Interface
Figure 29 shows a serial interface between the AD5310 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5310, while the MOSI output drives
the serial data line of the DAC. The SYNC signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that its CPOL bit is a 0 and its CPHA
bit is a 1. When data is being transmitted to the DAC, the SYNC
line is taken low (PC7). With this 68HC11/68L11 configuration,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5310, PC7 is left low after the first eight bits are transferred,
a second serial write operation is performed to the DAC, and
PC7 is taken high at the end of this procedure.
Figure 29. AD5310 to 68HC11/68L11 Interface
AD5310 to 80C51/80L51 Interface
Figure 30 shows a serial interface between the AD5310 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD5310
while RXD drives the serial data line of the part. The SYNC
signal is again derived from a bit-programmable pin on the
port. In this case, Port Line P3.3 is used. When data is to be
transmitted to the AD5310, P3.3 is taken low. The 80C51/80L51
transmits data only in 8-bit bytes; therefore, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this
cycle. The 80C51/ 80L51 outputs the serial data in a format that
has the LSB first. The AD5310 requires that the MSB of data be
received first. The 80C51/80L51 transmit routine should take
this into account.
Figure 30. AD5310 to 80C51/80L51 Interface
AD5310 to MICROWIRE Interface
Figure 31 shows an interface between the AD5310 and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5310 on the rising edge of the SK.
Figure 31. AD5310 to MICROWIRE Interface
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