參數(shù)資料
型號(hào): AD5310BRMZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 13/16頁
文件大?。?/td> 0K
描述: IC DAC 10BIT R-R W/BUFF 8-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,000
設(shè)置時(shí)間: 6µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
AD5310
Data Sheet
Rev. B | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. SOT-23
Figure 4. SOIC
Table 4. SOT-23 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VOUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
2
GND
Ground Reference Point for All Circuitry on the Part.
3
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and VDD should be decoupled to GND.
4
DIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
5
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 30 MHz.
6
SYNC
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
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