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參數(shù)資料
| 型號(hào)： | AD5311BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-bit, 500 MSPS Analog-to-Digital Converter with Buffered Input 80-HTQFP |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大小： | 178K |
| 代理商： | AD5311BRM |
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REV. 0
AD5301/AD5311/AD5321
–10–
X
X
PD1
PD0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DB0 (LSB)
DB15 (MSB)
DATA BITS
Figure 23a. AD5301 Input Shift Register Contents
X
X
PD1
PD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DB0 (LSB)
DB15 (MSB)
DATA BITS
Figure 23b. AD5311 Input Shift Register Contents
X
X
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB0 (LSB)
DB15 (MSB)
DATA BITS
Figure 23c. AD5321 Input Shift Register Contents
SERIAL INTERFACE
2-WIRE SERIAL BUS
The AD5301/AD5311/AD5321 are controlled via an I
2
C-
compatible serial bus. The DACs are connected to this bus as
slave devices (no clock is generated by the AD5301/AD5311/
AD5321 DACs).
The AD5301/AD5311/AD5321 has a 7-bit slave address. In the
case of the 6-pin device, the 6 MSBs are 000110 and the LSB is
determined by the state of the A0 pin. In the case of the 8-pin
device, the 5 MSBs are 00011 and the 2 LSBs are determined
by the state of the A0 and A1 pins. A1 and A0 allow the user to
use up to four of these DACs on one bus.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high to low transition on the SDA
line occurs while SCL is high. The following byte is the ad-
dress byte which consists of the 7-bit slave address followed
by an R/
W
bit (this bit determines whether data will be read
from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/
W
bit is high, the master will read
from the slave device. However, if the R/
W
bit is low, the
master will write to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an Acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL.
3. When all data bits have been read or written, a STOP condi-
tion is established by the master. A STOP condition is de-
fined as a low-to-high transition on the SDA line while SCL
is high. In Write mode, the master will pull the SDA line
high during the 10th clock pulse to establish a STOP condi-
tion. In Read mode, the master will issue a No Acknowledge
for the 9th clock pulse (i.e., the SDA line remains high). The
master will then bring the SDA line low before the 10th clock
pulse and then high during the 10th clock pulse to establish a
STOP condition.
In the case of the AD5301/AD5311/AD5321, a write operation
contains two bytes whereas a read operation may contain one or
two bytes. See Figures 24 to 29 below for a graphical explana-
tion of the serial interface.
A repeated write function gives the user flexibility to update the
DAC output a number of times after addressing the part only
once. During the write cycle, each multiple of two data bytes
will update the DAC output. For example, after the DAC has
acknowledged its address byte, and receives two data bytes, the
DAC output will update after the two data bytes, if another two
data bytes are written to the DAC while it is still the addressed
slave device, these data bytes will also cause an output update.
Repeat read of the DAC is also allowed.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Figure 23 illustrates the
contents of the input shift register for each part. Data is loaded
into the device as a 16-bit word under the control of a serial
clock input, SCL. The timing diagram for this operation is
shown in Figure 1. The 16-bit word consists of four control bits
followed by 8, 10 or 12 bits of data, depending on the device
type. MSB (Bit 15) is loaded first. The first two bits are “don’t
cares.” The next two are control bits that control the mode of
operation of the device (normal mode or any one of three
power-down modes). See Power Down Modes section for a
complete description. The remaining bits are left-justified DAC
data bits, starting with the MSB and ending with the LSB.
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