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參數(shù)資料
| 型號： | AD5311BRTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT 2WIRE W/BUF SOT23-6 |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.4mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 143k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
| 其它名稱： | AD5311BRTZ-REEL7DKR |
AD5301/AD5311/AD5321
Rev. B | Page 13 of 24
THEORY OF OPERATION
The AD5301/AD5311/AD5321 are single resistor-string DACs
fabricated on a CMOS process with resolutions of 8/10/12 bits,
respectively. Data is written via a 2-wire serial interface. The
devices operate from single supplies of 2.5 V to 5.5 V and the
output buffer amplifiers provide rail-to-rail output swing with
a slew rate of 0.7 V/μs. The power supply (VDD) acts as the
reference to the DAC. The AD5301/AD5311/AD5321 have
three programmable power-down modes, in which the DAC
can be turned off completely with a high impedance output,
or the output can be pulled low by an on-chip resistor (see the
Power-Down Modes section).
DIGITAL-TO-ANALOG
The architecture of the DAC channel consists of a resistor string
DAC followed by an output buffer amplifier. The voltage at the
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
N
DD
OUT
D
V
2
×
=
where:
N = DAC resolution
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0–255 for AD5301 (8 bits)
0–1023 for AD5311 (10 bits)
0–4095 for AD5321 (12 bits)
DAC
REGISTER
RESISTOR
STRING
OUTPUT BUFFER
AMPLIFIER
REF(+)
REF(–)
GND
VDD
VOUT
00
92
7-
02
4
Figure 24. DAC Channel Architecture
RESISTOR STRING
The resistor string section is shown in Figure 25. It is simply
a string of resistors, each with a value of R. The digital code
loaded to the DAC register determines at what node on the
string the voltage is tapped off to be fed into the output ampli-
fier. The voltage is tapped off by closing one of the switches
connecting the string to the amplifier. Because it is a string
of resistors, it is guaranteed monotonic over all codes.
R
TO OUTPUT
AMPLIFIER
009
27
-02
5
Figure 25. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output volt-
ages to within 1 mV from either rail, which gives an output range
of 0.001 V to VDD 0.001 V. It is capable of driving a load of
2 kΩ to GND and VDD, in parallel with 500 pF to GND. The
source and sink capabilities of the output amplifier can be seen
in Figure 14.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 μs with the output unloaded.
POWER-ON RESET
The AD5301/AD5311/AD5321 are provided with a power-on
reset function, ensuring that they power up in a defined state.
The DAC register is filled with zeros and remains so until a
valid write sequence is made to the device. This is particularly
useful in applications where it is important to know the state
of the DAC output while the device is powering up.
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