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| 型號： | AD5314BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT QUAD VOUT 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 143k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5304/AD5314/AD5324
Data Sheet
Rev. H | Page 14 of 24
THEORY OF OPERATION
FUNCTIONAL DESCRIPTION
The AD5304/AD5314/AD5324 are quad, resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. Each contains four output buffer amplifiers and
is written to via a 3-wire serial interface. They operate from single
supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7 V/μs. The four
DACs share a single reference input pin. The devices have pro-
grammable power-down modes, in which all DACs can be turned
off completely with a high impedance output.
Digital-to-Analog
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure 30
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
N
REF
OUT
D
V
2
where
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0–255 for AD5304 (8 bits)
0–1023 for AD5314 (10 bits)
0–4095 for AD5324 (12 bits)
N = DAC resolution.
REFIN
OUTPUT BUFFER
AMPLIFIER
RESISTOR
STRING
DAC
REGISTER
INPUT
REGISTER
VOUTA
0
09
29
-0
30
Figure 30. DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 31. It is simply a
string of resistors, each of value R. The digital code loaded to the
DAC register determines at which node on the string the voltage
is tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
R
TO OUTPUT
AMPLIFIER
00
92
9-
03
1
Figure 31. Resistor String
DAC Reference Inputs
There is a single reference input pin for the four DACs. The
reference input is not buffered. The user can have a reference
voltage as low as 0.25 V or as high as VDD because there is no
restriction due to the headroom or footroom requirements of
any reference amplifier. It is recommended to use a buffered
reference in the external circuit (for example, REF192). The
input impedance is typically 45 kΩ.
Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD when
the reference is VDD. It is capable of driving a load of 2 kΩ to
GND or VDD, in parallel with 500 pF to GND or VDD. The source
and sink capabilities of the output amplifier can be seen in the
plot in Figure 15.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs.
POWER-ON RESET
The AD5304/AD5314/AD5324 are provided with a power-on reset
function, so that they power up in a defined state. The power-on
state uses normal operation and an output voltage set to 0 V.
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
SERIAL INTERFACE
The AD5304/AD5314/AD5324 are controlled over a versatile,
3-wire serial interface that operates at clock rates up to 30 MHz
and are compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
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