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參數(shù)資料
| 型號(hào)： | AD5315BRM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 427K |
| 代理商： | AD5315BRM-REEL |
REV. F
–12–
AD5305/AD5315/AD5325
Pointer Byte Bits
The following is an explanation of the individual bits that make
up the pointer byte.
X
Don’t care bits.
0
Reserved bits, must be set to 0.
DACD
1: The following data bytes are for DAC D.
DACC
1: The following data bytes are for DAC C.
DACB
1: The following data bytes are for DAC B.
DACA
1: The following data bytes are for DAC A.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for
this operation is shown in Figure 1. The two data bytes consist
of four control bits followed by 8, 10, or 12 bits of DAC data,
depending on the device type. The first two bits loaded are PD1
and PD0 bits that control the mode of operation of the device.
See the Power-Down Modes section for a complete description.
Bit 13 is
CLR
, Bit 12 is
LDAC
, and the remaining bits are left-
justified DAC data bits, starting with the MSB. See Figure 7.
CLR
0: All DAC registers and input registers are filled with
zeros on completion of the write sequence.
1: Normal operation.
LDAC
0: All four DAC registers and, therefore, all DAC outputs
simultaneously updated on completion of the write
sequence.
1: Only addressed input register is updated. There is no
change in the contents of the DAC registers.
Default Readback Condition
All pointer byte bits power up to 0. Therefore, if the user initiates a
readback without writing to the pointer byte first, no single DAC
channel has been specified. In this case, the default readback
bits are all 0, except for the
CLR
bit, which is a 1.
Multiple-DAC Write Sequence
Because there are individual bits in the pointer byte for each DAC,
it is possible to write the same data and control bits to 2, 3, or 4
DACs simultaneously by setting the relevant bits to 1.
Multiple-DAC Readback Sequence
If the user attempts to read back data from more than one DAC
at a time, the part will read back the default, power-on reset
conditions, i.e., all 0s except for
CLR
, which is 1.
PD0
CLR
LDAC
D7
D6
D5
D4
PD1
LSB
MSB
8-BIT AD5305
PD0
CLR
LDAC
D9
D8
D7
D6
PD1
PD0
D11
D10
D9
D8
PD1
MOST SIGNIFICANT DATA BYTE
DATA BYTES (WRITE AND READBACK)
LSB
MSB
10-BIT AD5315
LSB
MSB
12-BIT AD5325
CLR
LDAC
LEAST SIGNIFICANT DATA BYTE
8-BIT AD5305
D3
D2
D1
D0
0
0
0
0
D5
D4
D3
D2
D1
D0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
LSB
MSB
LSB
MSB
10-BIT AD5315
LSB
MSB
12-BIT AD5325
Figure 7. Data Formats for Write and Readback
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