參數(shù)資料
型號(hào): AD5315BRM
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
中文描述: SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO10
封裝: MO-187BA, MSOP-10
文件頁數(shù): 10/20頁
文件大?。?/td> 427K
代理商: AD5315BRM
REV. F
–10–
AD5305/AD5315/AD5325
FUNCTIONAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. Each contains four output buffer amplifiers
and is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/
μ
s.
The four DACs share a single reference input pin. The devices
have three programmable power-down modes, in which all
DACs may be turned off completely with a high impedance
output, or the outputs may be pulled low by on-chip resistors.
Digital-to-Analog Section
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure 4
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
V
V
D
OUT
REF
N
=
×
2
I
DD
( A)
F
300
350
600
400
450
500
550
V
DD
= 5V
V
DD
= 3V
TPC 19. I
DD
Histogram with
V
DD
= 3 V and V
DD
= 5 V
V
DD
= 5V
T
A
= 25 C
V
REF
(V)
F
0.02
–0.020
1
3
0.01
–0.01
4
6
0
2
5
TPC 22. Full-Scale Error vs. V
REF
1 s/DIV
2.48
2.49
V
O
2.47
2.50
TPC 20. AD5325 Major-Code
Transition Glitch Energy
50ns/DIV
1
TPC 23. DAC-to-DAC Crosstalk
FREQUENCY (Hz)
10
–40
10
–20
–30
0
–10
d
100
1k
10k
100k
1M
10M
–50
–60
TPC 21. Multiplying Bandwidth
(Small-Signal Frequency Response)
where
D
= decimal equivalent of the binary code, which is loaded to
the DAC register:
0–255 for AD5305 (8 bits)
0–1023 for AD5315 (10 bits)
0–4095 for AD5325 (12 bits)
N
= DAC resolution
INPUT
REGISTER
REFIN
OUTPUT BUFFER
AMPLIFIER
V
OUT
A
RESISTOR
STRING
DAC
REGISTER
Figure 4. DAC Channel Architecture
相關(guān)PDF資料
PDF描述
AD5305ARM 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305ARM-REEL7 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305BRM-REEL 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305BRM-REEL7 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
AD5315ARM 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
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